Questa Verification IP Workshop
System on a chip (SOC) design trends continue to migrate toward platform-based designs built around standard interfaces and utilizing an ever-increasing number of reusable design IP components. A major challenge for the industry is verifying IP blocks, subsystems, and SOCs containing IP. Mentor Graphics® provides a complete and valuable tool, Questa® Verification IP, to help address today's design verification challenges and achieve first-pass success.
This workshop provides an in-depth look at Questa Verification IP (QVIP). QVIP provides a comprehensive test suite, a test plan derived from the protocol specification, assertion-based checks to ensure protocol compliance, and transaction-level debug. QVIP promotes utilization of reusable test bench building blocks, is in compliance with industry standards and protocols, and is ready to deploy in verification environments employing advanced methodologies such as UVM.
Using QVIP, you will be able to meet your verification goals more rapidly, at a higher level of abstraction, and in a manner promoting re-use. The workshop will focus on AMBA® AXI, a widely utilized protocol.
Who Should Attend
- Verification engineers and managers
What You Will Learn
- How QVIP can help you verify your design
- Common QVIP usage scenarios for an AXI-based DUT
- How to deploy QVIP in monitor (passive) mode within an existing test bench to enable checking for protocol compliance and determination of functional coverage
- How to deploy QVIP in active mode within a UVM-based test bench to achieve 100% coverage
- Transaction-level debug of protocol errors