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Mentor Forum for Verification 2014 India

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Overview

Location:
Hotel Vivanta by Taj, MG Road
No.1, MG Road
Bangalore

Verification is a challenge be it IC or FPGA based designs. Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Verification teams are trying to use multiple tools and methodologies to achieve verification closure in the current aggressive time to market schedules. Some of these challenges are related to low power verification, verification management and planning, managing all the coverage data, having a common debug environment,  effective reuse “vertically” and horizontally” and verifying complexities such as coherency etc. On the other end you have FPGA designer spending hours together on debugging simple issues on the board and in the lab. How and what can cater to make verification more effective across the entire gamut from FPGA designs to complex SoC’s and from simple IP’s to System level? If you want to know the answer to this question, this Verification Forum is for you.

Don't miss out on this excellent networking and learning opportunity.

What You Will Learn

  • Current SoC Verification Challenges
  • Enhance your verification productivity
  • Tools and techniques to manage/automate verification regression runs
  • How to use Low Power Verification methodology
  • How to automate, track and accelerate coverage closure
  • How you can leverage on Formal techniques to close verification
  • How to use emulation to accelerate your verification

Who Should Attend

  • Verification Engineers and Managers

About the Presenters

Presenter Image Nithin Maiya Kumar

Manager, Verification – BMOD  Ericsson
Nithin has 12 years of experience in the field of functional verification in complex SOCs mainly for mobile market. Working with Ericsson modems for 3 years managing the entire functional verification unit in BMOD – Bangalore . Specializes in complex low power SOC & SubSystem verification involving new verification methodologies . Prior to Ericsson  he was working for Texas Instruments ,India

Presenter Image Manish Singh

Front End CAD Director, Qualcomm
Manish is the FrontEnd CAD Director for Qualcomm Bangalore. He has over 20 years of experience in the semiconductor industry. In the past he has worked with Intel, Sun Microsystems, and Cadence. His CAD experience.

Presenter Image John Lenyo

Vice President and General Manager Design Verification Technology Division, Mentor Graphics

John received a BSEE from Rutgers University and an MBA from the Harvard Business School. John has an extensive background in the electronics and semiconductor industries having worked at IBM as an ASIC designer and in various marketing roles at Sun Microsystems, Metaphor Corporation, Logic Modeling, and Synopsys. John moved to Mentor as director of marketing for functional verification technologies including ModelSim, Questa and the 0-In products in 1999 and was promoted to general manager of the Design Verification Technology division in May 2008. He is a member of the Board of Directors of Calypto Design Automation and the Board of Trustees of the Oregon Ballet Theatre.

Products Covered

Agenda

details

   
8:30 AM 9:30 AM Registration
9:30 AM 10:15 AM Navigating the Perfect Storm: Verification Challenges and Solutions
John Lenyo, VP and GM DVT, Mentor Graphics
10:15 AM 10:45 AM Industry Keynote: Finding Answers to SoC Verification Challenges
Manish Singh, Front End CAD Director, Qualcomm
10:45 AM 11:15 AM Addressing Complex Verification Challenges using Mentor Graphics Solutions
Nithin Kumar Maiya, Manager , Verification – BMOD , Ericsson
11:15 AM 11:30 AM Coffee/Tea Break
11:30 AM 12:15 PM Injecting Automation into FPGA Verification
12:15 PM 1:00 PM Block to System Level Verification
1:00 PM 2:00 PM Lunch
2:00 PM 2:45 PM Low Power Verification from RTL to Gate using UPF
2:45 PM 3:30 PM Emulation: The Veloce Ecosystem – Capabilities, Flows and Solutions
3:30 PM 3:45 PM Coffee/Tea Break
3:45 PM 4:30 PM Automate "Formal"ly - New applications that enhance verification
4:30 PM 5:15 PM Hit or Miss ? How do I Automate my Verification flow and Manage it systematically?
5:15 PM 5:30 PM Wrap & Closing
 
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