Mentor Forum for Verification 2013 India
As we enter the era of SoCs, verification complexity will be driven by increased design complexity of multiple cores running many applications to deliver on-demand content in consumer devices such as tablets and smartphones. As a result of the increased verification complexity, verification challenges continue to grow exponentially. Through advances in technology and methodology, verification productivity has improved dramatically over the past decade. Yet, the continuing growth in the size of verification teams and the amount of project time dedicated to verification indicate the need for greater advances in productivity. It is clear that verification must be transformed in order to deliver the productivity that will enable the next generation of multi-core SoC consumer electronics. Innovative technologies that enable you to track and close your coverage closure challenges are required. As the impact of software in electronic systems grows, verification solutions must expand to enable co-verification with advanced verification technology. Comprehensive solutions and methodology will integrate these innovative tools and enable real-time progress tracking, trend analysis and increased automation and efficiency of the verification process.
If you need to transform your verification processes to dramatically boost productivity, radically decrease time-to coverage, and more effectively and efficiently manage your verification processes, then this Verification seminar is for you.
What You Will Learn
- Current SoC Verification Challenges
- Enhance your verification productivity
- Tools and techniques to manage/automate verification regression runs
- How to use Low Power Verification methodology
- How to automate, track and accelerate coverage closure
- How you can leverage on Formal techniques to close verification
- How to use emulation to accelerate your verification
Who Should Attend
- Verification Engineers and Managers
- Questa® inFact
- Questa® Advanced Simulator
- Questa® CoverCheck
- Questa® Power Aware Simulator
- Questa® Verification Management
8:45 AM Registration
The keynote will review the results of the most recently completed global study on design and verification practices and trends. The observed convergence of SoC design practices toward a common methodology will be covered. Lastly, the impact that industry-based standards development practices have had will be examined to understand recent adoption velocity improvements from the verification study results and how continued improvements can continue to accelerate adoption of emerging and new design and verification techniques.
SOC definition “SOC =System On Chip” in today’s scenario has got changed to “SOC=Technology + Demand”. SOC is an IC that integrates the major functional elements of a complete end product in to single chip.
Today a revision of silicon not only costs millions of dollars but also impacts time to market, quality and customer commitments. As the sub-micron technology shrinks in die size, this enables the architects to push more and more functionality in to a single chip. Today’s SOCs are very sensitive to “Time to Market” and “COST”. This poses lot of challenges on SOC schedule and quality. One of the schedule intensive activity in SOC life cycle is verification. This is also one of the major parameter that defines the quality of SOC. First time working SOC requires robust module level, sub-system level, performance level, and system level verification strategy to uncover most of the bugs before tapeout. For a successful verification strategy, the test bench and test cases needs to scalable, configurable, and supports reuse. The verification strategy with a robust test bench need to give out coverage at different levels, enable the tester to merge them and get a combined coverage. This combined coverage should be able to identify the holes in verification and cover them to give confidence for tape out.
This keynote will talk about Key challenges in SOC verification and ways to address these challenges.
Effective application of reuse methods in verification environments across different levels, not only improves productivity, but reduces time for verification closure and hence enabling more products to hit the market on time. Reuse of block-level to subsystem-level verification environments and sub-system level to the SOC level is well supported by advanced verification methodologies such as UVM/OVM. Choice of configurable VIPs, in combination with custom built components like scoreboards, coverage model etc, are key elements in making the reuse work seamlessly. By following the guidelines presented in this keynote, we can get a well defined recipe for hitting the desired goals – “abracadabra” – Isn’t this like MAGIC ? Let’s see how it works.
11:00 AM Break
High speed serial interconnect bus fabric is the SoC backbone, managing dataflow and keeping up with the dynamic bandwidth requirements of high speed applications. Verification of high speed interconnect IPs presents critical challenges not only in terms of complying with standards, but also in ensuring that the design is robust and flexible enough to handle and manage a large amount of time-critical data transfers. Acquiring such expertise requires years of verification experience. In this session, Silicon IP and platform enabled solution provider Mobiveil shares its story of verifying high speed bus protocol standards like PCI Express and Serial RapidIO, including what considerations are required when verifying high speed designs. In addition, Mobiveil highlights the benefits of using the Mentor Graphics Questa Verification Platform, including Questa Advanced Simulator, Questa CoverCheck, and Questa Clock-Domain Crossing (CDC) Verification, which together facilitates smart functional verification, debug and reporting of the high speed designs.
12:05 PM UVM Based Advanced Verification
12:50 PM Lunch
With the Questa functional verification platform, achieving coverage closure means much more than just generating stimulus and hoping for coverage results. Questa eases testbench programming by leveraging its robust Verification IP Library, automates the generation of coverage models, and intelligently generates stimulus to ensure that high test quantity does not come at the expense of high test quality. Questa also reduces the time needed to manage regression testing and merge coverage results from hours to minutes. Attend this session to learn how Questa can help you can gain 10X to 100X in verification productivity by
- Automatically generating SystemVerilog covergroups and coverage models
- Intelligently generating stimulus that achieves target coverage closure faster, and increases overall coverage
- Reducing nightly regression setup time, and automating results merging and coverage analysis
Adding to the stress of verifying today’s SoC’s is the fact that designing for low power using the latest techniques adds another layer of complexity to the tasks of design and verification. This session will discuss a lower power verification methodology using the IEEE 1801 UPF(Unified Power Format) standard that enables greater productivity and reuse through hierarchical decomposition which allows defining and verifying power intent at the IP level and reusing that intent at the SoC level.
3:20 PM Break
In the world of ever increasing verification complexity, is anything getting any easier? For some good news on this front, join us for this session where we will examine solutions which add automation to the verification process. Focus areas include: reset and X-state propagation, enhanced coverage through automatic property generation, handling the convergence of multiple clock and power domains, and more!
4:25 PM Verification Using Emulation
5:10 PM Wrap-Up & Lucky Draw
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.
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