Verification Today and Tomorrow - Technology Seminar
Recent industry studies point to an accelerated rate at which traditional system-level functionality is being integrated into a single SoC. To address this increasing complexity brought on by higher levels of integration, the industry has been forced to adopt more holistic design and verification flows. Join us for the day to hear the latest on Coverage Closure, Low Power, SoC verification techniques and a session that will explore some of the practical approaches, verification challenges for reuse, scalability and performance validation challenges and solutions for AMBA® 4 ACE™ & AMBA® 5 CHI cache coherency systems.
Beyond Theory, Standards, and the Status Quo, Presented by Harry Foster, Mentor Graphics
Harry Foster is Chief Scientist for the Mentor Graphics Design Verification Technology Division. He holds multiple patents in verification and has co-authored seven books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions in developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
Verification of ARM AMBA® 5 CHI Cache Coherent Systems, Presented by Ashley Stevens, ARM
Ashley has been with ARM since 1995 and has a background in SoC design and architecture in a variety of technical and marketing roles within ARM. In 2009 he moved his family from the ARM Cambridge HQ to the ARM Austin Texas facility and is now an FAE supporting system IP, AMBA and SoC architecture. Previously he worked for Acorn Computers (where the ARM processor was originally developed), Tadpole Computer and Marconi Defence. He has a Bachelor of Engineering (B.Eng) in Computer Engineering from Queen Mary, University of London. He has 8 granted patents with several more published applications and is a senior member of the IEEE.
Who Should Attend
- Verification Engineers and Managers
8:30 - 9:00 Registration and Continental Breakfast
9:00 - 9:50 Beyond Theory, Standards, and the Status Quo
Recent industry studies point to an accelerated rate at which traditional system-level functionality is being integrated into a single SoC. To address this increasing complexity brought on by higher levels of integration, the industry has been forced to adopt more holistic design and verification flows. For example, it is no longer sufficient to simply track coverage purely at the IP-level—ignoring other interactions related to software and power. In this keynote, Foster presents recent trends that have shaped today's emerging SoC flows, and argues that we are now beyond theory in terms of rising complexity, beyond arguing over who won the standards wars, and beyond surviving by maintaining the status quo.
9:50 - 10:50 Achieving Coverage Closure of SoC Designs
Achieving coverage closure means much more than just generating stimulus and hoping for results. It requires intelligently targeting coverage objectives while employing an integrated combination of simulation, emulation, and formal verification engines. This session will show how the Questa and Veloce platforms can help you achieve coverage goals 10X to 100X faster, by utilizing common stimulus technology, coverage models, and verification IP; and applying them at the IP block, subsystem, and full-system levels.
10:50 - 11:00 Break
11:00 - 12:30 UPF-Based Block to System Low Power Verification, Joint Presentation with Abhishek Ranjan from Calypto
Power management is critical for portable electronic systems and involves both hardware and software. Hardware aspects include power domain partitioning, isolation, level shifting, state retention, and power control logic. Software involves drivers that direct hardware power control logic to ensure that system resources are powered appropriately in each functional mode.Thorough verification of a power-managed system requires verification of interactions between software and hardware aspects of power management. Visualization of these interactions is essential to efficiently debug power management problems and ensure full coverage. The ability to verify such interactions in both simulation and emulation enables incremental power aware verification at various integration levels. Not only is power management verification required but developers of low power systems require in depth power analysis at multiple stages of the design process in order to give them feedback on how to improve and modify their power management to meet their designs power requirements. This session covers how the combination of the Questa Platform, Veloce emulation and additional power analysis tools provide a comprehensive UPF-based low power verification and power analysis solution that goes from block to system including both HW and SW.
12:30 - 1:00 Lunch Break
1:00 - 1:50 Verification of ARM AMBA® 5 CHI Cache Coherent Systems
This session will introduce the ARM system IP components available for AMBA® 5 CHI cache coherent compute sub-systems and present some of the verification practices needed for their efficient validation and verification. We explore some of the practical approaches, verification challenges for reuse, scalability and performance validation challenges and solutions for AMBA® 4 ACE™ & AMBA® 5 CHI cache coherency systems that ARM is enabling through its ARM Connected Community Partners.
1:50 - 2:40 Holistic ARM Based SoC Verification
Ensuring correct functionality of a SoC requires a holistic approach. Through comprehensive easy-to-use verification components, automated & intelligent test solutions, and high performance verification engines, this session will cover the critical verification solutions & capabilities needed for your SoC; interconnect subsystem, processor subsystem, to peripherals and special function accelerator blocks.
Raising Productivity Using Abstract UVM Stimulus and Intelligent Automation
This webinar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation...
Automating the Creation of Your UVM Register Model
This webinar will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register...
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.