Mentor.com :: Functional Verification Resources

On-demand Web Seminar:Configuration in UVM

Wed, 01 Feb 2012 01:34:29 GMT

News Article:Altera Adopts the Mentor Graphics Veloce Hardware Emulator to Accelerate Time-to-Market for their Next-Gen Products

Tue, 24 Jan 2012 14:00:00 GMT

WILSONVILLE, Ore., January 24, 2012—Mentor Graphics Corp. (NASDAQ: MENT), a leader in high-performance system verification solutions, today announced that Altera, a leader in innovative custom logic solutions, has adopted the Veloce® emulator platform for the accelerated verification of its next-generation products. Altera’s solutions target a wide range of applications, including automotive, broadcast, computer and storage, consumer, industrial, medical, military, test and measurement, wireless, and wireline.

Blog Post:SystemC 2011 Standard Published

Dennis Brophy — Mon, 16 Jan 2012 16:00:06 GMT

IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that

News Article:Mentor Graphics Partners with Freescale to Deliver Vista-based Virtual Prototype Solution for Freescale Processors

Thu, 12 Jan 2012 21:00:00 GMT

WILSONVILLE, Ore., January 12, 2012 — Mentor Graphics Corp. (NASDAQ: MENT) today announced it has signed a preferred, long-term partnership agreement with Freescale Semiconductor to deliver state-of-the-art, high-speed simulation platforms for Freescale’s QorIQ® P-Series, AMP and QorIQ Qonverge™ product lines of multicore embedded processors. In support of this partnership, Mentor® now offers a powerful virtual prototyping environment and enabling technologies which allow Freescale customers to achieve early, more efficient software integration and accelerate their product delivery cycles.

Blog Post:Verification solutions that help reduce bug cost

Harry Foster — Sun, 08 Jan 2012 17:57:59 GMT

I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive it is to fix. In fact, the general rule-of-thumb is that the cost to fix a bug increases by an order of magnitude as a project progresses from one milestone to the next. Bugs found before simulation obviously have the lowest cost. Bugs found at block or subsystem simulation are generally easier

News Article:Mentor Graphics Delivers Emulation-Ready Transactors for the Accelerated Verification of SoCs

Mon, 19 Dec 2011 14:00:00 GMT

WILSONVILLE, Ore., December 19, 2011—Mentor Graphics Corp. (NASDAQ: MENT), a leader in high-performance system verification solutions, today announced the availability of a set of protocol transactors for use with the Veloce® hardware emulation platform. The Veloce transactors enable the use of stimuli generated by modern simulation testbenches, including SystemVerilog/OVM and UVM, SystemC, and ‘C’- based environments, and apply them to the design-under-test (DUT) running in the Veloce hardware. This allows engineers to stress-test a DUT that includes one or more protocol interfaces on their SoC at orders of magnitude faster than simulation. Since the connection between the testbench and the Veloce transactors are at a transaction-level, rather than signal interface, a high level of performance is delivered.

Blog Post:Instant Replay for Debugging SoC Level Simulations

Mark Olen — Wed, 14 Dec 2011 01:16:27 GMT

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires. They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time. But watching at home on television, we get the luxury of viewing multiple replays of events in question

Blog Post:2011 IEEE Design Automation Standards Awards

Dennis Brophy — Mon, 05 Dec 2011 16:37:40 GMT

The DASC Participates in IEEE Standards Association Gala Event The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA on 4 December 2011. Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples. The

On-demand Web Seminar:More UVM Registers

Wed, 30 Nov 2011 18:53:29 GMT

The inclusion of the Register Layer was one of the most requested features of UVM. This session will expand on the introductory session delivered in October to discuss how to implement registers and also review score-boarding at the register layer.

Blog Post:Overridden with Overrides

Dave Rich — Tue, 22 Nov 2011 19:38:50 GMT

The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent objects. In