Mentor.com :: Functional Verification Resources

Event:Advanced FPGA Verification Lunch & Learn Seminar

Wed, 15 May 2013 07:00:00 GMT

This seminar will focus on three major topics related to improving design verification through process automation. Each topic is a train journey with three stops. We will look at assertions, coverage and UVM Express. The stops will help you get the most out of your tools and methodology. Regardless of whether you ride the train to the last stop or jump off at the first, what you learn will make you better off than before you started the journey.

Event:Advanced FPGA Verification Seminar

Sun, 05 May 2013 07:00:00 GMT

This seminar will focus on three major topics to improve design verification by injecting automation into the process.

On-demand Web Seminar:Advanced UVM Debugging

Tue, 30 Apr 2013 16:21:35 GMT

This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.

Industry Article:Knock Down the Wall to SoC Integration

Tue, 30 Apr 2013 07:00:00 GMT

Knock Down the Wall to SoC Integration

News Article:Mentor Graphics Accelerates SoC and Embedded System Delivery with a Native Embedded Software Environment for Pre- and Post-Silicon Development, Embedding QEMU, SystemC and Emulation

Mon, 22 Apr 2013 13:00:00 GMT

WILSONVILLE, Ore., April 22, 2013—Mentor Graphics Corporation today announced release of the Mentor® Embedded Sourcery™ CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon.

News Article:Mentor Graphics Delivers Simulation and Emulation Solutions to Verify Serial Attached SCSI Products

Mon, 08 Apr 2013 13:00:00 GMT

WILSONVILLE, Ore., April 8, 2013 — Mentor Graphics Corp. (NASDAQ: MENT), a leader in advanced system verification solutions, today announced hardware and software solutions to accelerate the verification of Serial Attached SCSI (SAS) second-generation (Gen 2) products, having speeds up to 6Gbps. Using the Mentor® verification solutions, designers can test their SAS Gen2 devices integrated on their System-on-Chip (SoC) designs, and develop and test their software drivers and applications prior to silicon being available.

News Article:Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution

Thu, 04 Apr 2013 13:00:00 GMT

WILSONVILLE, Ore., April 4, 2013 — Mentor Graphics Corp. today announced availability of the first, comprehensive IP to System, UPF-based low-power verification flow.

On-demand Web Seminar:The 2012 Wilson Research Group Functional Verification Study

Fri, 29 Mar 2013 15:57:11 GMT

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster highlights the key findings from the 2012 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.

White Paper:Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation

Fri, 15 Mar 2013 07:00:00 GMT

Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification and validation platforms have been developed as separate flows, preventing reuse of modules and methods between the two. As a consequence, various customized verification and validation platform features must be devised and implemented to verify complex, highly integrated System on Chip (SoC) designs. Bringing these two flows together would save an immense amount of duplicate effort and time while potentially reducing the introduction of errors, since less code needs to be developed and maintained.

Industry Article:Best Practices in Verifying Low-Power Designs

Thu, 14 Mar 2013 07:00:00 GMT