Mentor.com :: Functional Verification Resources

Event:Introduction to Code Coverage

Wed, 12 Jun 2013 07:00:00 GMT

Wspólnie z firmą Gamma (dystrybutorem narzędzi HDL & PCB na terenie Polski) mamy przyjemność zaprosić Państwa na webinar pod tytułem - wprowadzenie do Code Coverage.

News Article:Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs

Mon, 03 Jun 2013 19:00:00 GMT

WILSONVILLE, Ore., June 3, 2013 —Mentor Graphics Corp. (NASDAQ: MENT) today announced that cache coherent interconnect subsystem verification has been added to the Questa® and Veloce® platforms.

Blog Post:Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy

Tom Fitzpatrick — Fri, 31 May 2013 19:17:13 GMT

Hi Everyone, Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles: Interviewing a Verification Engineer

Blog Post:IEEE 1801™-2013 UPF Standard Is Published

Dennis Brophy — Thu, 30 May 2013 04:51:11 GMT

Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance

White Paper:FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions

Sun, 19 May 2013 15:00:00 GMT

This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting simulation debugging time in half, as well as finding very complex bugs that are likely to escape traditional simulation without assertions.

Blog Post:Part 1: The 2012 Wilson Research Group Functional Verification Study

Harry Foster — Wed, 08 May 2013 14:47:09 GMT

Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs. This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing

Blog Post:Those nasty wire’s and reg’s in Verilog

Dave Rich — Fri, 03 May 2013 20:07:36 GMT

A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to pick up SystemVerilog

On-demand Web Seminar:Advanced UVM Debugging

Tue, 30 Apr 2013 16:21:35 GMT

This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.

Industry Article:Knock Down the Wall to SoC Integration

Tue, 30 Apr 2013 07:00:00 GMT

Knock Down the Wall to SoC Integration

Blog Post:Getting AMP’ed Up on the IEEE Low-Power Standard

Dennis Brophy — Mon, 29 Apr 2013 23:20:59 GMT

Power Aware Verification Course Modules Released I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to