FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference. This is orders of magnitude faster than traditional gate-level simulation - designs that take days or weeks can be verified in hours or even minutes using FormalPro.
Quickly prove that a design is functionally identical - compare RTL to gate netlist for synthesis, gate to gate netlists for layout spins. Use one tool and flow for all your designs.
Rapid verification of multi-million gate designs and dramatic reduction in verification time using static formal verification techniques. Fastest route to correct design with a comprehensive debug tool that identifies the location/cause of errors and the unique “what-if” capability to investigate design modifications within the existing verification session.
FormalPro and Precision Synthesis provide unique integration for equivalence checking of FPGAs. An FVI setup file, containing synthesis optimization information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist equivalence checking. AMD Xilinx and Microchip (Microsemi) FPGA devices are supported in this flow.
FormalPro and Precision Hi-Rel is the industry’s only integration that proves functional equivalence between RTL and the mitigated FPGA design. An FVI setup file, containing synthesis optimization and mitigation information, is auto-generated by Precision, enabling a reliable push-button RTL to gate netlist to mitigated gate netlist equivalence checking.
Join the discussion on new topics, features, content and technical experts.
Access detailed user application notes, training resources and more.
Helping you achieve maximum business impact by addressing complex technology and enterprise challenges with a unique blend of development and design experience and methodology expertise.