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FormalPro

Equivalence Checking

FormalPro™ is the Mentor Graphics solution for gate-level regression testing of ASICs and ICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference.

This technique is orders of magnitude faster than traditional gate-level simulation. Designs that take days or even weeks to simulate with gate-level simulation can be verified in hours or even minutes using FormalPro. For designs greater than 100,000 gates, FormalPro is an essential verification tool in an ASIC design flow.

Where to Use FormalPro

  • FormalPro is a Regression Testing Tool
  • That verifies all stages of gate-level implementation of a design
  • From synthesis through to tape out

Features

  • Dramatically Reduces ASIC/FPGA Verification Time
  • Compares two designs
    - RTL to gate for synthesis and ECOs
    - Gate to gate for layout spins
    - RTL to RTL for language conversion
  • Highest capacity tool
    - Verifies multi-million gate
    - ASIC's as one
  • Fastest route to correct design
    - Exact location of errors
    - Tests fixes within the verification session
  • Advanced FPGA Support
    - Xilinx, Altera, Actel
    - FVI and VIF automated setup files
    - Huge productivity boost
  • GUI for design entry and initial debug
  • Command line mode for regression testing
  • Constraint language and TCL scripting
  • Incremental Verification
    - Recompile only design that has changed
    - Restart at intermediate points

Low Power Solution

Low Power designs give you the added boost you need to address power at every stage in the design flow – from ESL through functional verification all the way to physical implementation. Low Power Solutions

 
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