FormalPro™ is the Mentor Graphics solution for gate-level regression testing of ASICs and ICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference.
This technique is orders of magnitude faster than traditional gate-level simulation. Designs that take days or even weeks to simulate with gate-level simulation can be verified in hours or even minutes using FormalPro. For designs greater than 100,000 gates, FormalPro is an essential verification tool in an ASIC design flow.
- Dramatically Reduces ASIC/FPGA Verification Time
- Compares two designs
- RTL to gate for synthesis and ECOs
- Gate to gate for layout spins
- RTL to RTL for language conversion
- Highest capacity tool
- Verifies multi-million gate
- ASIC's as one
- Fastest route to correct design
- Exact location of errors
- Tests fixes within the verification session
- Advanced FPGA Support
- Xilinx, Altera, Actel
- FVI and VIF automated setup files
- Huge productivity boost
- GUI for design entry and initial debug
- Command line mode for regression testing
- Constraint language and TCL scripting
- Incremental Verification
- Recompile only design that has changed
- Restart at intermediate points
Questa® Advanced Simulator
product overview: The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
product overview: ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.
product overview: Superior quality results, award-winning analysis to eliminate defects & advanced operator inference to enable FPGA vendor-independent design.