ICanalyst CB

Automating the Verification of Complex Analog and Mixed-Signal System-on-Chip Designs

The ICanalyst CB verification flow available in Mentor's ICanalyst™ is a batch and interactive platform for automating the verification of complex analog and mixed-signal System-on-Chip designs.

Modern SoC designs are very large mixed-signal designs. System level verification becomes mandatory because of the high cost of respins.

On the one hand, simulating SoC designs using solely pure digital models is fast but inaccurate. On the other hand, simulating SoC designs with only transistor level models is too slow. A common verification strategy is to mix and match abstract models and detailed models, depending on the test point, in order to optimize performance while maintaining accuracy for decisive criteria. This verification strategy is known by many names, but we call it Checkerboard Verification (CB). CB can, however, lead to a combinational explosion of different design configurations and testbenches.

The ICanalyst CB verification flow manages the details of CB, by automating the creation, simulation and analysis of results for potentially hundreds or thousands of design runs, taking advantage of any existing compute farm. Additionally, ICanalyst CB will manage your process libraries revisions to make regression testing effortless, and will help you with creating documentation for design reviews and knowledge sharing among your design communities.