The consumer electronics market is demanding new, innovative products at an ever faster rate. Increasingly ‘digital convergence’ is driving new innovative products with rich functionality that often includes Internet browsing and high definition and/or streaming video with ever decreasing power consumption objectives.
Products are often based on application specific platforms — an integrated, configurable set of IPs targeted to a specific functionality, be it wireless or digital TV, with a rapidly increasing amount of software content required to gain competitive advantages in the consumer experience. Validating that architectural hardware and software deliver an optimal experience demands rapid analysis of overall system performance. Early detection and resolution of performance-taxing behavior enables robust platform design delivery. Effective functional verification is critical to meet the schedule deadlines set for product introduction.
Design projects face these common, unique verification challenges:
Ensure power requirements are met
Power is a core driver that determines the success of most products in the consumer electronics market. This is true not only for highly portable devices, but also for may other applications as well (for example large server farms). Mentor’s solution for system-level power estimation (Vista) and accurate functional verification of low power designs (Questa) are critical to ensure that your low power design meets its objectives.
Pre-silicon system validation
With increased software applications within many consumer electronics products, designers need to validate the complete system (i.e. hardware and the software) before committing to tape out or FPGA production. Mentor offers a set of solutions that range from system behavioral modeling to support for transaction-level analysis in Vista. Hardware/software co-verification at the RTL is available using Seamless, and high capacity and performance emulation are delivered by Veloce.
Full system/chip level verification
Chip level verification, specifically for the large application platforms underlying many of the high-volume consumer electronics products, is very challenging. Clearly a solution that delivers simulation capacity and performance and handles multiple levels of abstraction (TLM, RTL, gate), like Questa, is just the starting point. The advanced architectures used to deliver high performance and low power also require the comprehensive solutions for clock domain verification available in Questa CDC, software integration with Questa Codelink, and mixed signal verification through Questa ADMS.
Productive testbench development
Today, the testbench for a complex chip can easily require more lines of code than the design, and, hence, methodologies and tools that focus on highly productive testbench development are critical. This is where the Universal Verification Methodology (UVM) plays a crucial role. By defining the structure of a testbench it UVM harnesses the power of constrained-random testing and coverage driven verification. Mentor offers industry leading tools for automating UVM testbench creation, development, and analysis to reduce UVM testbench creation time and ease the adoption of UVM. Integrating Questa inFact intelligent stimulus modules and Mentor Verification IP enables a complete and robust solution.
Reuse of verification effort
Effective reuse of the verification effort is the biggest productivity booster and has been a primary objective in the development of the Universal Verification Methodology (UVM). With the UVM establishing architecture for the testbench, it also has established a market for verification IP. Mentor’s Verification IP library of VIP fit seamlessly in UVM-based testbenches and offer support for many of the popular standards. While at the same time, through our third party Questa Vanguard program, many more VIPs are available from our partners. Moreover, engineers looking for solutions for C-based testing will benefit greatly from Questa Codelink while executing on the their Processor-driven Verification Methodology (PVM).
Verification schedule predictability
Schedule predictability is clearly important in any project; however in the consumer electronics area this is particularly critical, since many products need to hit firm deadlines. Accurate metrics related to the verification process and the use of these metrics to manage the verification process are the key to getting visibility into the schedule. This is what the Questa verification management capability and Unified Coverage DataBase (UCDB) are about. With requirements tracing and other tools like Questa inFact, Mentor Verification IP, Questa Formal Verification, and Questa CDC also interfacing with the UCDB, a complete metric driven solution is delivered, greatly enhancing schedule predictability.
Digital and analog integration
With analog components present in virtually every chip, an accurate, high-performance solution for mixed signal verification is a must. In the Mentor verification platform this is provided by Questa ADMS and the ICAnalyst CB set of products. Their seamless integration with the Questa platform ensures a full simulation solution for all abstraction levels, including analog.