Networking and Data Communication
Efficiently moving and managing data across the globe is at the core of providing the competitive business and gratifying consumer experience demanded in today’s connected world. To deliver this experience, companies around the world are delivering powerful solutions, leveraging a multitude of sophisticated technology combining dedicated hardware and software solutions. Products often contain a large amount of application specific logic, dedicated hardware to implement complex communication protocols, and dedicated architectures.
Design projects face these common unique verification challenges:
Early architectural validation
With high software content commonplace in many consumer electronics products, designers need to validate the complete system, i.e. hardware and software, before committing to tape out. Mentor offers a set of solutions here that range from abstract modeling and support for transaction-level modeling with Vista, processor-based hardware verification with Codelink, hardware/software co-verification with Seamless, and high capacity and high performance emulation with Veloce.
Productive testbench development
Today the testbench for a complex chip can easily require more lines of code than the design, and, hence, methodologies and tools that focus on highly productive testbench development are critical. This is where the Universal Verification Methodology (UVM) plays a crucial role. Defining the structure of a testbench, it harnesses the power of constrained-random testing and coverage driven verification. Mentor offers the industry's best execution platform for OVM with Questa. Along with tools to efficiently create, develop and automate testbenches while leveraging the industry’s most powerful stimulus generator, Questa inFact engineers today are provided the tools to boost their productivity.
Ability to run “real world” traffic
Being able to run real world traffic is often needed to ensure not only correct operation but also that the multiple data streams are processed by the device within the specifications for the respective classes of services the device needs to support. There are two ways real world traffic realistically can be handled: building a prototype or using emulation. Veloce is a prime example of a high performance, high capacity emulation environment that handles real world data streams, and its unique ability to handle multiple asynchronous clocks makes it a prime solution to verify today’s networking and communication devices.
Perform efficient coverage data management
The sheer amount of data produced by the suites of verification tools used to verify today’s chips requires a high capacity Unified Coverage DataBase (UCDB) to store all the coverage data. This is exactly what Questa’s UCDB is all about. It delivers a very high capacity, compact, binary database to store the coverage data and, through Questa’s verification management tools, allows a wide range of operations like merging, filtering, and prioritizing on this coverage data.
Validate hardware software integration
Today’s advanced networking and communication devices are a combination of hardware and software, and a methodology that simulates both simultaneously is essential. Not only is the software used to configure the chip to support the selected protocols, often the software provides the higher layers of these protocols as well. Only an integrated approach can accomplish this. Mentor’s Seamless product is a proven solution that delivers such an integrated approach
Effectively verify multi-clock designs
Today’s communication and networking chips need to support many protocols, many of these protocols have their own standardized frequencies, and chips routinely have to extract the actual clock frequency from the incoming data. This combined with high performance and low power requirements means a single chip can have many (sometimes in the hundreds) separate clock domains. Solutions like Questa CDC help designers verify the correct implementation of the interaction between these clock domains.