Semiconductor & IP Development
Today’s advanced processor and IP cores and application platforms use advanced techniques and sophisticated micro architectures to achieve the high performance and low power required by most products. The chip complexity and transistor count enabled by the advanced 65 and 45 nm technology nodes results in daunting verification challenges that can only be addressed efficiently by a proven, comprehensive verification solution.
Mentor’s functional verification platform is a prime example of such a solution. Mentor’s functional verification platform delivers a synergistic set of methodologies, tools, and metrics to plan, execute, and guide the verification process. By offering high-capacity and high-performance simulation, formal verification, and emulation, designers are enabled to readily choose the core verification engines most suited for the verification tasks at hand, while selecting the best methodology for the verification tasks at hand.
Design projects face these common, unique verification challenges:
Achieve a very high degree of confidence in functional correctness
To reduce the probability that bugs work their way into silicon, designers complement the baseline RTL simulation platforms with solutions that focus on specific tasks or classes of bugs; for example scenario generation, low power verification, and clock domain crossing verification. Mentor’s comprehensive verification platforms deliver just that. Centered around the Questa® and Veloce simulation platforms, solutions for clock domain verification (with Questa® CDC), formal verification (with Questa® Formal), and sophisticated stimulus generation (with inFact®) support the advanced methodologies —such as Assertion-Based Verification (ABV) and the Universal Verification Methodology (UVM) many designers use today to verify their chips.
Achieving coverage closure
Today’s modern verification processes are largely based on the coverage-driven verification methodology. Based on a well defined verification plan, the coverage goals you need to achieve are set and during the course of the project the actual coverage of these goals is measured. Once the goals are achieved, you are done. Achieving coverage closure is the number one verification challenge. Mentor has dedicated solutions to support this coverage-driven flow. The powerful verification management capabilities in Questa automate the coverage driven methodology, while unique tools like Questa inFact and the verification IP in the Questa MVC library focus on delivering the most effective stimulus. Plus, the integration of Questa Formal Verification with simulation enables engineers to reach the hard to reach coverage points.
Perform effective bock/module level verification
Many of the new blocks designed today are designed with reuse in mind. This poses specific challenges. Clearly the confidence in the correctness of the block needs to be very high, yet the block may have many user selectable configuration parameters. In general, this means that simulation alone is not sufficient, since the number of permutations that need to be verified is simply too large. To this end many engineers add formal verification to their existing simulation-based verification flows, thus achieving the next level of confidence: that the block is implemented correctly. This is where our products, Questa Formal Verification and Questa CDC, often come into the picture.
Ensure power requirements are met
Power is a core driver that determines the success of many products. This is true not only for highly portable devices, but also for may other applications as well (for example large server farms). Mentor’s solution for system-level power estimation (Vista) and accurate functional verification of low power designs (Questa) are critical to ensure that your low power design meets its objectives.
Create a highly productive testbench development process
Today, the testbench for a complex chip can easily require more lines of code than the design, and, hence, methodologies and tools that focus on highly productive testbench development are critical. This is where the Universal Verification Methodology (UVM) plays a crucial role. By defining the structure of a testbench it harnesses the power of constrained-random testing and coverage driven verification, Mentor offers the industry’s best execution platform for UVM with Questa along with tools to efficiently create, develop and automate testbenches, including Questa inFact for powerful stimulus generation. In addition, Codelink enables engineers to use their software as a testbench to quickly verify their processor based design hardware, and Seamless helps them ensure that the software and hardware are seamlessly integrated.
Achieve accurate schedule predictability
Accurate metrics related to the verification process and the use of these metrics to manage the verification process are the key to getting visibility into the schedule. This is what the Questa verification management capability and Unified Coverage DataBase (UCDB) are about. With other tools like Questa inFact, Mentor VIP, Questa Formal Verification, and Questa CDC also interfacing with the UCDB, a complete metric-driven solution is delivered, greatly enhancing schedule predictability.
Perform efficient coverage data management
The sheer amount of data produced by the suites of verification tools used to verify today’s chips requires a high capacity Unified Coverage DataBase (UCDB) to store all the coverage data. This is exactly what Questa’s UCDB is all about. It delivers a very high capacity, compact, binary database to store the coverage data and, through Questa’s verification management tools, allows a wide range of operations like merging, filtering, and prioritizing on this coverage data.