Intelligent Testbench Automation
Mentor Graphics Questa® inFact is the industry’s most advanced testbench automation solution. It targets as much functionality as traditional constrained random testing, but achieves coverage goals 10X to 100X faster.
This enables engineering teams to complete their functional verification process in less time, and/or to expand their coverage goals, testing functionality that previously fell below the cut line. Questa inFact also generates tests that an engineer might not envision, reaching difficult corner cases that alternative testing techniques typically miss.
Recently announced, intelligent software driven verification ("iSDV") has been added to the Questa inFact functionality to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. iSDV bridges the gap between IP block and full system level verification by applying intelligent testbench automation to hardware/software verification at the system level. While writing directed tests in C to verify single-core designs at the system level was challenging, today's multi-core multi-threaded designs has made this process virtually impossible. Questa iSDV automates this process.
Using Questa inFact technology ensures high quality products
Accelerating Coverage Closure with Intelligent Testbench Automation
On-demand Web Seminar: The Questa Questa inFact Intelligent Testbench Automation solution generates stimulus according to the user s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases....
Questa inFact: Verifying a DMA Controller
Technology Overview: Questa inFact is a stimulus-generation tool that accelerates functional coverage closure. In this demo, you will see how Questa inFact is applied to verification of a DMA controller. The key features of...
Revolutionary results are not enough. Advanced technology must fit into existing processes and flows. Questa inFact can be integrated into current verification environments with little to no disruption. It supports UVM (and OVM) methodologies; standard languages such as SystemVerilog, SystemC, C/C++; and even other proprietary testbench languages. And if you are looking for an incremental way to move from a proprietary language to SystemVerilog, Questa inFact can provide a natural bridge, offering the benefits of a standard language while supporting legacy verification IP written in a non-standard language.
The number of companies turning to Questa inFact is growing exponentially. The minimum result experienced to date has been 10X faster achievement of target coverage. But many companies have gained 100X or better. Why such dramatic gains in productivity? The nature of constrained random testing lends itself to uncontrollable redundancy. While some repetition can be valuable, Questa inFact enables engineers to control the amount of redundancy desired, while generating the same or a higher quantity of tests.
One networking company was able to achieve more coverage in 48 CPU hours with Questa inFact than they achieved with constrained random testing in 3175 hours. That’s a gain of 66X. A consumer electronics company was stuck at 60% of their target coverage after 8 weeks of simulation on 6 CPUs. With Questa inFact they were able to achieve 100% of their target coverage in just 36 hours on the same 6 CPUs. That’s a gain of 37X plus 40% more coverage. In both cases, the time needed to integrate Questa inFact was less than a couple of days.