inFact

Intelligent Testbench Automation

Mentor Graphics inFact intelligent testbench automation solution is the first to use a graph-based approach to accelerate functional coverage closure and find design bugs early in the verification process.

With inFact, the user can comprehensively describe the scenarios in which a device is expected to operate. This often equates to stimulus sequences to be applied within a verification system and the expected responses from the DUT or other devices connected with the testbench. inFact applies intelligent algorithms to generate these sequences, monitor the results, and ensure generation of non-redundant sequences.

Language Support

Simulation tasks in inFact are written in Verilog, SystemVerilog, C/C++, or SystemC – engineers are not required to learn a new language. Testbench sequences created by inFact contain stimulus and checks, and trigger assertions – in the same way other testbench techniques do. inFact works with the industry-standard simulators, including Questa, ModelSim, and others.

Benefits

  • Intelligent testbench modules automatically create test sequences, data, and checks dynamically during simulation
  • Efficient stimulus generation creates non-redundant test sequences
  • Functional coverage closure acceleration at the module, subsystem, and system-levels
  • Distributed simulation enables linear speed-up of coverage closure across multiple servers
  • Verification scenarios are compactly described by rules and compiled into graphs, dramatically reducing testbench code
  • Accelerates functional coverage closure by at least an order of magnitude compared to traditional constrained random testbenches
  • Dramatically improves testbench effectiveness, efficiency, and productivity while reducing testbench code
  • Eliminates redundancy in test sequence generation
  • Efficiently achieves targeted coverage goals within user’s allocated simulation time
  • Finds more design bugs earlier in the verification process
  • Influences the test sequences applied based on user’s verification goals

Related Products

  • QuestaQuesta is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
  • 0-In Formal VerificationThe 0-In® Formal verification solution offers the highest capacity and performance available to help you find your most complex bugs.
  • 0-In Clock-Domain CrossingDesigners increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains.

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