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Methodologies for Functional Verification

Verification Methodologies form the backbone of a solid verification strategy. Mentor Graphics is actively driving advanced methodologies and their standardization across the industry.


Assertion-based verification (ABV) is a methodology in which designers use assertions to capture specific design intent and, either through simulation, formal verification, or emulation of these assertions, verify that the design correctly implements that intent. Learn more

The UVM is the first Industry-Standard verification methodology delivering an open and unified class library and methodology for interoperable verification IP and testbenches. Based on OVM and written in SystemVerilog 1800, the UVM is the culmination of collaboration among user and vendor companies in Accellera. Learn more

Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor-driven test benches into the existing verification methodology enables real-world verification and extensive reuse of testbench software throughout the project. Learn more

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