Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor-driven test benches into the existing verification methodology enables real-world verification and extensive reuse of testbench software throughout the project. One of the limitations to effective utilization of processor-driven tests has been the difficulty of debugging software in a processor running in a logic simulator.
Today’s complex circuit designs with embedded processors require the execution of instructions in software to meet the maximum coverage of an SoC. There are several classic approaches to achieve these goals, including driving bus cycles into the hardware design, execution on a full functional model, compiled drivers to target, and testbenches in C or assembly code.
However, this approach has the drawback of being incomplete. The tests do not cover the entire interaction between the processor and external logic. And there is no software execution as part of the entire system. Since the end product is processor driven, the “real simulation” approach of instructions executing on a fully-functional processor model and driving bus cycles into the design is superior to traditional bus-functional models.
A processor-driven testbench addresses the desire to have system stimulus and monitoring using a fully-functional processor model. The test instructions drive stimulus into the system when they are executed, and the results of the test are read and monitored by other instructions in the test.
Processor-driven tests offer the greatest reuse potential during all phases of the project.
|High-Level Synthesis||RTL/Gate Simulation||Emulation||Prototype or FPGAs|| |