The Universal Verification Methodology (UVM) is a standard verification methodology from the Accellera Systems Initiative that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
While many companies, even competitors, contributed to the development of UVM in Accellera, Mentor continues to play a leading role in its proliferation, both through the committee and in the marketplace. In response to our customers' needs, Mentor has recently announced two new UVM initiatives to expand the reach of UVM in the industry. UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation. UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing, as well as a command API, between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily to develop integrated verification environments where you take advantage of the strengths of each language to maximize your verification productivity.
Read detailed information on OVM/UVM and to download the new UVM/OVM Online Methodology Cookbook and Kits on the UVM/OVM Verification Methodology resource site.
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
Using Questa Verification IP you can reduce the overall testbench development time and complete more verification with less effort.