UVM/OVM
The Universal Verification Methodology (UVM) is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to enable creation of robust, reusable, interoperable verification IP and testbench components.
One of the most novel and exciting aspects of UVM is how it was developed. Rather than being developed by a single EDA vendor and rolled out as part of a marketing campaign, it was developed by a collection of industry experts representing microprocessor companies, networking companies, verification consultants, as well as EDA vendors. All the work was done under the auspices of Accellera. Under the umbrella of a standards organization, companies, even competitors, were able to come together in a collaborative environment to address the technical challenges of building a sophisticated verification methodology. The result is a powerful, multi-dimensional software layer and methodology for building verification environments. UVM is truly an industry initiative, one in which Mentor is proud to participate.
Learn More
Read detailed information on OVM/UVM and to download the new UVM/OVM Online Methodology Cookbook and Kits on the UVM/OVM Verification Methodology resource site.
Products
-
Questa® Advanced Simulator
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
-
Questa Verification IP
Using Questa Verification IP you can reduce the overall testbench development time and complete more verification with less effort.
More Scalable Verification Methodologies
Datasheets
- Veloce Family (PDF, 1mb)
- Certe Testbench Studio (PDF, 786kb)
- Transforming Verification: Questa Verification Platform (PDF, 2mb)
ToolBox
- White Paper: UVM: The Next Generation in Verification Methodology
- White Paper: Improving Efficiency, Productivity, and Coverage Using SystemVerilog OVM Registers
- White Paper: Towards an Object-Oriented Design Methodology Using SystemVerilog
- White Paper: Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification
Contact Mentor Graphics
- Request Information or call toll free: 1-800-547-3000
