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Power Efficient Design Challenges and Trends

Description: This webinar will cover key aspects to the forces from a technology and market perspective that are driving designers towards better energy efficient designs.



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Why is OVM and Hardware Acceleration Such a Viable Solution

Description: OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system...


Products: Questa

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Verification Strategy for Mixed-Signal SoCs

Description: This Tuesday Tech Talk will look into various tools available for Analog design verification, help understand underlying techniques and how they fit into SoC verification and how to take advantage of those...


Products: Questa ADMS

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How do you determine the right way to improve your verification capability?

Description: Whatever you are designing, verification is becoming an increasingly complex and time consuming activity. Determining how best to improve your verification capability can seem almost as difficult doing...


Products: Questa

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Questa: SystemVerilog Verification from Requirements to Coverage Closure

Description: SystemVerilog delivers advanced functional verification techniques in an industry standard language. However, the effective, predictable verification of electronic systems takes much more than constrained-random...


Products: Questa

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ModelSim DE: Debug productivity and observability in a ModelSim package

Description: ModelSim now offers support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support. The web seminar will review these new features and more.



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Verification Management: Gather, Analyze and Report

Description: This Questa Verification Management webinar will give you confidence that you can efficiently gather information, effectively analyze and easily report progress against your verification plan's goals.


Products: Questa

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Introduktion av ModelSim DE, Support för Xilinx SecureIP och Assertion-Baserad Verifiering med SystemVerilog och PSL

Description: Du känner säkert till att ModelSim är simulatorn som ledande elektronikföretag inom alla industrigrenar väljer. Förrutom singel kärne simulator finns ett intuitivt lättanvänt...



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Introducing ModelSim DE, Support for Xilinx SecureIP and Assertion-Based Verification with SystemVerilog and PSL

Description: ModelSim now offers support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support. The web seminar will review these new features and more.



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Finding and Solving Metastability Problems Introduced by Multiple Clock Domains

Description: Finding and Solving metastability problems introduced by multiple clock domains.


Products: 0-In Clock-Domain Crossing

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Showing: 1-10 of 48 total resources
1-10 | 11-20 | 21-30 | 31-40 | 41-48
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