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UVM Debug46:19On-demand Web Seminar: UVM class-based testbenches have become as complex as the designs they are meant to verify, and are, in fact, large object-oriented software designs. As such, new debugging techniques and tools must be... 46:19 Tags: Debug, OVM, UVM |
Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs35:48On-demand Web Seminar: ARM is leading the industry in multi-core design with its Cortex™-A series applications processors including both its high-performance ARM Cortex™-A15 and its high-efficiency ARM Cortex-A7.... 35:48 Tags: Questa, Questa Codelink, SoC, SoC Level Verification |
UVM Connect48:07On-demand Web Seminar: UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect allows you easily... 48:07 Tags: Certe Testbench Studio, OVM, Questa® Advanced Simulator, Register Package, UVM |
UVM Express46:53On-demand Web Seminar: UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of... 46:53 Tags: Certe Testbench Studio, OVM, Questa® Advanced Simulator, Register Package, UVM |
More UVM Registers42:11On-demand Web Seminar: The inclusion of the Register Layer was one of the most requested features of UVM. This session will expand on the introductory session delivered in October to discuss how to implement registers and also... 42:11 Tags: OVM, Questa® Advanced Simulator, Registers, UVM |
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Questa CDC Verification Demo10:08Product Demo: This is a demo of Mentor's CDC verification solution. During the demonstration we will show you why Mentor is a leader in CDC verification and how our solution will help you find bugs missed by all other... 10:08 Tags: CDC, CDC Verification, Questa CDC, Questa® CDC Verification |
Intro to UVM Registers46:32On-demand Web Seminar: The inclusion of the Register Layer was one of the most requested features of UVM. This session will provide an introduction to the Register Layer and show you how to get started writing tests and sequences... 46:32 Tags: OVM, Questa® Advanced Simulator, Register Package, UVM |
Sequence Layering01:01:43On-demand Web Seminar: Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components... 01:01:43 Tags: Layering, Questa® Advanced Simulator, Sequence |
Verifying Complex SoC Designs with Questa Codelink33:38On-demand Web Seminar: This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments. 33:38 Tags: Debug, Questa Codelink |
Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar26:52On-demand Web Seminar: This webinar focuses on the how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior. We show through a set of detailed examples how non-determinism caused... 26:52 Tags: Debug, Questa® CDC Verification |
Improving Quality and Time-to-Market with Formal Verification44:16On-demand Web Seminar: This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic... 44:16 Tags: Assertion-Based Verification, Questa® Formal Verification |
