Accelerating Coverage Closure with Intelligent Testbench Automation
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Mentor Graphics has a proven methodology to accelerate functional coverage closure, freeing up resources to achieve more verification. Questa Ultra’s Intelligent Testbench Automation solution generates stimulus according to the user’s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases. The result is 10x to 100x faster functional coverage closure.
Duration: 24:05
Tags: Coverage Closure, Questa® inFact, Testbench Automation
View On-demand Web Seminar (Opens in New Window/External URL)
Details
Overview
Achieving functional coverage closure in today’s complex designs is challenging and time consuming. It is common for a verification team to spend a disproportionate amount of time attempting to achieve the last 20% of functional coverage, by identifying corner cases manually, struggling to create overly complex constraints, and often times resorting to writing lengthy directed tests to target these cases.
Mentor Graphics has a proven methodology to accelerate functional coverage closure, freeing up resources to achieve more verification. Questa Ultra’s Intelligent Testbench Automation solution generates stimulus according to the user’s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases. The result is 10x to 100x faster functional coverage closure.
What You Will Learn
- How to achieve your targeted functional coverage 10x to 100x times faster
- How to ensure that each and every test sequence generated has a purpose
- How to achieve the most verification per cycle of simulation
- How to extend this capability across an entire simulation server farm
- How to do this while reusing 95% or more of your existing verification IP
About the Presenter
Matthew Ballance
Matthew Ballance is a Verification Technologist at Mentor Graphics for the Design Verification Technology division, specializing in the inFact Intelligent Testbench Automation tool. He has 12 years of experience in the EDA industry, and has previously worked in the areas of HW/SW Co-verification and transaction-level modeling.
Who Should View
- Design and Verification Engineers and Managers
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