Active Power Management Verification with Power Aware Simulation
On-demand Web Seminar
Abstract
Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances in process technology, minimizing power consumption is now mandatory. This webinar presents Questa Power Aware Simulation and describes how it is being used today to verify active power management in complex SoC designs. The webinar will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device and how Questa Power Aware simulation enables visualization and debugging of active power management and its effect on design functionality. The webinar will also describe how other tools within the Questa Verification Platform are used in a comprehensive low power verification flow.
Duration: 36:48
Opens in New Window/External URL
Tags
Details
Overview
Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances in process technology, minimizing power consumption is now mandatory. This webinar presents Questa Power Aware Simulation and describes how it is being used today to verify active power management in complex SoC designs. The webinar will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device and how Questa Power Aware simulation enables visualization and debugging of active power management and its effect on design functionality. The webinar will also touch on how other tools within the Questa Verification Platform are used in a comprehensive low power verification flow.
What You Will Learn
- Active Power Management, Power Mgmt Architecture and Behavior, IEEE 1801 UPF, PA Verification for Blocks and SoCs
About the Presenter
Erich Marschner
Erich is the Solutions Manager for Low Power and Static/Formal Verification at Mentor Graphics.
Erich has 25+ years in EDA driving development of advanced design and verification:
- standards (IEEE 1076 VHDL, IEEE 1850 PSL, IEEE 1800 SystemVerilog, IEEE 1801 UPF)
- technology (behavioral synthesis, equivalence checking, behavior abstraction, formal verification, power aware simulation)
- and methodology (assertion-based verification, coverage-driven verification, verification planning, low power verification)
Previously Senior Architect at Cadence (’97-‘08), Fellow at COMPASS (’93-‘97), and Technical Director/President of CLSI (’86-‘93). Erich holds a BS Computer Science and BA Medieval Languages and Literature from Univ. of Maryland in 1980.
Who Should View
- Design and Verification Engineers and Managers
Related Resources
Multimedia
Advanced UVM Debugging
This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar
The 2012 Wilson Research Group Functional Verification Study
Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster...…View On-demand Web Seminar
Other Related Resources
Questa Essentials
Training Course: This course will teach you the benefits of Questa’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional...…View Training course
SystemC Advanced Verification
Training Course: This intensive, practical course is intended for engineers familiar with SystemC who have an interest in learning about the SystemC Verification Library (SCV) and verification techniques using the library.…View Training course
Unifying Hardware-Assisted Verification and Validation Using UVM and Emulation
White Paper: Successful approaches to improve verification productivity are to increase the speed of verification and begin validating software/hardware integration very early in the design process. Historically, verification...…View White Paper