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Active Power Management Verification with Power Aware Simulation



Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances in process technology, minimizing power consumption is now mandatory. This webinar presents Questa Power Aware Simulation and describes how it is being used today to verify active power management in complex SoC designs. The webinar will explain how IEEE Std 1801 UPF is used to define the power management architecture for a device and how Questa Power Aware simulation enables visualization and debugging of active power management and its effect on design functionality. The webinar will also touch on how other tools within the Questa Verification Platform are used in a comprehensive low power verification flow.

What You Will Learn

  • Active Power Management, Power Mgmt Architecture and Behavior, IEEE 1801 UPF, PA Verification for Blocks and SoCs

About the Presenter

Presenter Image Erich Marschner

Erich is the Solutions Manager for Low Power and Static/Formal Verification at Mentor Graphics.

Erich has 25+ years in EDA driving development of advanced design and verification:

  • standards (IEEE 1076 VHDL, IEEE 1850 PSL, IEEE 1800 SystemVerilog, IEEE 1801 UPF)
  • technology (behavioral synthesis, equivalence checking, behavior abstraction, formal verification, power aware simulation)
  • and methodology (assertion-based verification, coverage-driven verification, verification planning, low power verification)

Previously Senior Architect at Cadence (’97-‘08), Fellow at COMPASS (’93-‘97), and Technical Director/President of CLSI (’86-‘93).  Erich holds a BS Computer Science and BA Medieval Languages and Literature from Univ. of Maryland in 1980.

Who Should View

  • Design and Verification Engineers and Managers
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