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Advanced Formal Verification



In recent years, formal verification has emerged as an alternative approach that addresses the main limitation of simulation-based verification: checking a small fraction of the behaviours of non-trivial hardware designs. Formal verification consists of verifying that a design satisfies a given requirement for all legal input patterns. Formal verification has been successfully applied in the last few years and the scope of applications has dramatically increased.

What You Will Learn

  • When is a formal verification problem complex?
    • What has a verification tool to offer in this case?
    • What should/can the verification engineer do in this case?
  • Why is debugging difficult?
  • What is required in a mixed-language context?
  • How can formal verification be used as a complementary solution for simulation?

About the Presenter

Presenter Image Abdelouahab Ayari

Abdelouahab Ayari, Ph.D. is an application engineer for formal verification, clock domain crossing, and low power verification.

He received his doctor in formal verification at the University of Freiburg and worked for Micronas GmbH before joining Mentor Graphics.

He has over 8 years experience on Assertion-Based Verification (ABV) and supporting major customers in the area of formal verification across Europe

Who Should View

  • Verification Engineers
  • Formal Verification Methodologist

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