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Automating Code Coverage Closure with Questa CoverCheck



This webinar will introduce you to the Questa CoverCheck methodology that automates and accelerates the process of code coverage closure.

Code coverage is a metric used by the majority of today’s project teams with the goal of providing a quantitative measure for assessing their progress towards completeness. Typically, >90% of coverage items in a design are covered in a full regression, but it’s the process of analyzing that last ~10% which is problematic. Each uncovered point in the code must be reviewed to determine if it is safe to ignore or if the test environment must be enhanced to cover it, typically through writing directed tests. This is a manual process which typically takes multiple man-months of effort per design block. Questa CoverCheck automates this process by finding and reporting the unreachable goals that can be excluded and demonstrating how to hit the reachable ones, which guides the process of test creation.

What You Will Learn

  • Schedule predictability – save project time that would have been spent manually reviewing the coverage holes
  • Improved design quality – eliminate the danger of mistakenly ignored coverage holes
  • Improved metrics – tune coverage measurement to the relevant modes of operation of the design
  • Eliminate waiver maintenance – automatically update waivers to account for design changes

About the Presenter

Presenter Image Mark Eslinger

Mr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.

Who Should View

  • Verification Engineers and Managers
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