Automating Software-Driven Hardware Verification with Questa inFact
On-demand Web Seminar
Today’s complex designs increasingly include at least one, and often more, embedded processors. Given software’s increasing role in the overall design functionality, it has become increasingly important to leverage the embedded processors in verifying hardware/software interactions during system-level verification. Comprehensively verifying low-level hardware/software interactions early in the verification process helps to uncover bugs that otherwise would be uncovered during operating system or application bring-up – potentially in the lab. Characterizing, debugging, and correcting this type of bug is easier, faster, and thus less expensive, early in the verification cycle.
Recently announced, Questa inFact intelligent software-driven verification (iSDV) functionality enables automation of embedded C tests to comprehensively verify hardware/software integration in single- and multi-core SoC designs.
What You Will Learn
- Challenges of verifying SoC hardware/software integration
- How Questa inFact iSDV automates comprehensive hardware/software verification
- How iSDV helps to find hardware/software integration bugs early in simulation and emulation, instead of in the prototype lab
About the Presenter
Matthew Ballance is a Verification Technologist at Mentor Graphics for the Design Verification Technology division, specializing in the inFact Intelligent Testbench Automation tool. He has 12 years of experience in the EDA industry, and has previously worked in the areas of HW/SW Co-verification and transaction-level modeling.
Who Should View
- Verification Engineers and Managers
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