Sign In
Forgot Password?
Sign In | | Create Account

Clock-Domain Crossing Verification for FPGAs



This webinar talks about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your FPGA is free of CDC issues.

Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as ASIC designers are. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming to debug process in the lab.

Questa CDC supports the leading FPGA vendors.

What You Will Learn

  • Issues with clock domain crossings
  • How to avoid these issues
  • How to apply an automated verification solution to ensure your FPGA is free of CDC issues

About the Presenter

Presenter Image Chris Rockwood

Mr. Rockwood has over 20 years of experience in engineering design, customer support and marketing. In his current role as a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics, Mr. Rockwood focuses on assertion-based methods, formal verification and clock domain crossing verification. Prior to Mentor. Mr. Rockwood worked for several companies as an ASIC/FPGA designer, including Apple Computer, Motorola and Ardent Computer, where he was one of the first users of synthesizable Verilog and Synopsys Design Compiler in the late 1980s. Mr. Rockwood holds a B.S. in Electrical Engineering from Rice University in Houston, Texas.


Who Should View

  • Managers, designers, verification engineers of multi-clock designs

Related Resources


Advanced UVM Debugging

This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2.…View On-demand Web Seminar

The 2012 Wilson Research Group Functional Verification Study

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster...…View On-demand Web Seminar

The Questa Platform: Generating Coverage Models and Achieving Coverage Closure - DAC 2012

Recent industry surveys show that two-thirds of new design projects fall behind schedule due to verification. In addition, 70% of these designs fail at least once after verification is completed. With over...…View Technology Overview

Other Related Resources

Understanding electronic IP: common issues and how to find them

White Paper: Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology...…View White Paper

Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper

Applied Micro Circuits Corporation (AMCC)

Success Story: Applied Micro Circuits Corporation (AMCC) adopts Questa CDC for their complex clock domain crossing verification.…View Success Story

Online Chat