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Clock-Domain Crossing Verification for FPGAs



This webinar talks about the types of problems associated with clock domain crossings, the things you can do to avoid these issues, and how to apply an automated verification solution to ensure your FPGA is free of CDC issues.

Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as ASIC designers are. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming to debug process in the lab.

Questa CDC supports the leading FPGA vendors.

What You Will Learn

  • Issues with clock domain crossings
  • How to avoid these issues
  • How to apply an automated verification solution to ensure your FPGA is free of CDC issues

About the Presenter

Presenter Image Chris Rockwood

Mr. Rockwood has over 20 years of experience in engineering design, customer support and marketing. In his current role as a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics, Mr. Rockwood focuses on assertion-based methods, formal verification and clock domain crossing verification. Prior to Mentor. Mr. Rockwood worked for several companies as an ASIC/FPGA designer, including Apple Computer, Motorola and Ardent Computer, where he was one of the first users of synthesizable Verilog and Synopsys Design Compiler in the late 1980s. Mr. Rockwood holds a B.S. in Electrical Engineering from Rice University in Houston, Texas.


Who Should View

  • Managers, designers, verification engineers of multi-clock designs

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