Sign In
Forgot Password?
Sign In | | Create Account

Injecting Automation into Verification – Code Coverage

Details

Overview

Code Coverage is a method used to determine the effectiveness of the testbench for a piece of HDL code, which it does by measuring and indicating what percentage of the design was exercised by this testbench. The concept originally came from the software world where this is used in almost every software development organisation in their verification cycles. Despite the similarity of HDL code to software written in languages such as C, it is not so extensively used in HDL code verification.

Without code coverage the designer will find it hard (or impossible) to know if all aspects of the RTL code have been exercised by the testbench. Code Coverage is built into the simulator and it will tell the designer which areas have been exercised and, much more importantly, which have not. Without the use of Code Coverage it is highly likely that key parts of the functionality of a design have not been fully verified which leaves the possibility of bugs slipping through the scope of the regression tests.

What You Will Learn

  • What Code Coverage is
  • What it can tell you about your code and testbench
  • How it can be used within your verification environment

Who Should View

  • Design Engineers
  • Verification Engineers
  • Quality Engineers or Managers

Related Resources

Multimedia

Filling the Gap from DOORS Requirements through Component Design

IBM DOORS is nearly universally used by the Mil-Aero industry to capture and manage system level requirements. On the other hand, at the detail design stage DOORS is considered by most engineering teams...…View Technology Overview

Simplify FPGA Design with VHDL-2008

This FPGA webinar explores how VHDL-2008 can not only help simplify your HDL coding, but also help improve your overall design implementation.…View On-demand Web Seminar

DO-254 Evolution: Topics of Interest and Concern

DO-254 compliance has always been a moving target. Since its finalization in 2000 and then complete re-scoping at its invocation in 2005, to the latest changes (and inconsistencies) with the FAA and EASA...…View Technology Overview

Other Related Resources

When Spreadsheets Aren’t Enough

White Paper: Engineers writing embedded software for 32-bit microcontrollers at the STMicroelectronics campus in Agrate Brianza, Italy used Mentor Graphics' requirements tracing tool, ReqTracer, on a recent project....…View White Paper

FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions

White Paper: This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...…View White Paper

First time’s a charm for FPGA verification at Lockheed Martin Space Systems Company

Success Story: Lockheed Martin uses SystemVerilog, OVM and Mentor Graphics tools for first-pass FPGA verification success…View Success Story

 
Online Chat