Injecting Automation into Verification – Code Coverage
On-demand Web Seminar
Code Coverage is a method used to determine the effectiveness of the testbench for a piece of HDL code, which it does by measuring and indicating what percentage of the design was exercised by this testbench. The concept originally came from the software world where this is used in almost every software development organisation in their verification cycles. Despite the similarity of HDL code to software written in languages such as C, it is not so extensively used in HDL code verification.
Without code coverage the designer will find it hard (or impossible) to know if all aspects of the RTL code have been exercised by the testbench. Code Coverage is built into the simulator and it will tell the designer which areas have been exercised and, much more importantly, which have not. Without the use of Code Coverage it is highly likely that key parts of the functionality of a design have not been fully verified which leaves the possibility of bugs slipping through the scope of the regression tests.
What You Will Learn
- What Code Coverage is
- What it can tell you about your code and testbench
- How it can be used within your verification environment
About the Presenter
Neil holds a B.Eng in Electronic Engineering from Queen Mary College, University of London, and has over 20 years experience in ASIC and FPGA design. He worked initially for 8 years for several defence companies in the UK. From there, he went into applications engineering for first Actel and then Xilinx distributors where he supported many customers across the UK and Ireland. He then worked for 7 years for Saros Technology supporting numerous EDA vendors, including Mentor. Since joining Mentor Graphics in 2008, Neil has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects and giving technical presentations across Europe.
Who Should View
- Design Engineers
- Verification Engineers
- Quality Engineers or Managers
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