Configuration in UVM
On-demand Web Seminar
One of the key tenets of designing reusable testbenches is to make testbenches as configurable as possible. Doing this means that the testbench and its constituent parts can easily be reused and quickly modified.
This webinar will review the configuration database feature of UVM and show you how to organize your testbench to maximize flexibility. We will review how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT. The discussion will also cover how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
What You Will Learn
- Review the configuration database feature of UVM
- How to organize your testbench to maximize flexibility
- How to set up configuration objects for your environment and verification components
- How to use the configuration database to connect your verification components to your dut using virtual interfaces
- How to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
About the Presenter
Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.
Who Should View
- Design and Verification Engineers and Managers
This webinar will introduce you to abstract stimulus specification to provide more effective UVM tests that can be reused throughout your SoC flow and show you how Questa employs intelligent automation...…View On-demand Web Seminar
This webinar will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register...…View On-demand Web Seminar
Other Related Resources
White Paper: UVM is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to...…View White Paper
Training Course: This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the...…View Training course
White Paper: RTCA/DO-254 (also known as DO-254 in the US or ED-80 in Europe) provides guidelines to facilitate requirements-based design of airborne electronic hardware. Now mandated by the US Federal Aviation Association...…View White Paper