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Cookbook Recipes Beyond UVM: Effectively Modeling and Analyzing Coverage

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Overview

Believe it or not, methodology is more than just using UVM. With that in mind, we are expanding the scope of our “Recipe of the Month” webinars. This is the first session with this new focus.

As the saying goes, "What doesn't get measured might not get done." And that is certainly true when trying to determine a design project's verification progress, or trying to answer the question "Are we done?" Whether your simulation methodology is based on a directed testing approach or constrained-random verification, to understand your verification progress you need to answer the following questions:

  • Were all the design features and requirements identified in the testplan verified?
  • Were there lines of code or structures in the design model that were never exercised?

Coverage is the metric we use during simulation to help us answer these questions. Once coverage metrics become an integral part of our verification process, it opens up the possibility for more accurate project schedule predictions, as well as providing a means for optimizing our overall verification process. Unfortunately, using coverage effectively is a lot easier said than done. Recent survey data show that 72% of projects claim to be using functional coverage, but that includes projects that may only be using 9 coverage points for a multi-million gate design (an actual case).

This webinar will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage, and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret. From there, we will review several examples that illustrate effective functional coverage for various applications, including bus protocol coverage, register-based block-level coverage and datapath coverage. Please come and join us.

What You Will Learn

  • The different types of coverage that are available to keep track of the progress of the verification process
  • How to create a functional coverage model from a specification
  • How to implement functional coverage for different types of designs, via examples

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Who Should View

  • Verification Engineers and Managers

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