Easily Inspect & Find Defects in Your Processor-Based Design and Testbench

Overview

During this presentation, you will learn how Codelink accelerates the diagnostic phase of processor-based designs using processor-driven tests. A product demonstration is also performed.

If you are running processor-driven tests with hundreds of thousands of lines of test code in digital simulation on your processor-based design, you know how difficult and time-consuming it is to figure out what went wrong in a failing simulation. Manually slogging through log.EIS or other processor trace files, assembly listings, symbol tables, and logic simulation waveforms is slow and very inefficient.

Codelink provides processor debug views for source/assembly, registers, memories, variables, etc. that are completely synchronized with Questa/ModelSim logic waveforms. You can run Codelink during simulation; and, when running Codelink post-simulation, you can step forward and backward through the simulation in a matter of seconds.

Codelink connects to ARM, MIPS, or IBM PowerPC processors in design signoff model, RTL, or gate form, instantiated in a block- or chip-level simulation, and requires no change to the design or processor models. Simulation results with and without Codelink attached to the simulation are identical.

What You Will Learn

• How Codelink accelerates the diagnostic and debug phase of your processor-based design using processor-driven tests
• Benefits for a processor-driven verification methodology

Who Should View

• HW Verification Engineers of ARM, MIPS, or IBM PowerPC processor-based designs