Easily Inspect & Find Defects in Your Processor-Based Design and Testbench
Requires Flash Player.
If you are running processor-driven tests with hundreds of thousands of lines of test code in digital simulation on your processor-based design, you know how difficult and time-consuming it is to figure out what went wrong in a failing simulation. Manually slogging through log.EIS or other processor trace files, assembly listings, symbol tables, and logic simulation waveforms is slow and very inefficient. Codelink provides processor debug views for source/assembly, registers, memories, variables, etc. that are completely synchronized with Questa/ModelSim logic waveforms. You can run Codelink during simulation; and, when running Codelink post-simulation, you can step forward and backward through the simulation in a matter of seconds. Codelink connects to ARM, MIPS, or IBM PowerPC processors in design signoff model, RTL, or gate form, instantiated in a block- or chip-level simulation, and requires no change to the design or processor models. Simulation results with and without Codelink attached to the simulation are identical. In this seminar, you will learn how Codelink accelerates the diagnostic phase of processor-based designs using processor-driven tests. This seminar includes a product demonstration. Although this is a free online event, registration is required.
Duration: 31:27
Tags: Processor Driven Verification, Questa Codelink
View On-demand Web Seminar (Opens in New Window/External URL)
Details
Overview
During this presentation, you will learn how Codelink accelerates the diagnostic phase of processor-based designs using processor-driven tests. A product demonstration is also performed.
If you are running processor-driven tests with hundreds of thousands of lines of test code in digital simulation on your processor-based design, you know how difficult and time-consuming it is to figure out what went wrong in a failing simulation. Manually slogging through log.EIS or other processor trace files, assembly listings, symbol tables, and logic simulation waveforms is slow and very inefficient.
Codelink provides processor debug views for source/assembly, registers, memories, variables, etc. that are completely synchronized with Questa/ModelSim logic waveforms. You can run Codelink during simulation; and, when running Codelink post-simulation, you can step forward and backward through the simulation in a matter of seconds.
Codelink connects to ARM, MIPS, or IBM PowerPC processors in design signoff model, RTL, or gate form, instantiated in a block- or chip-level simulation, and requires no change to the design or processor models. Simulation results with and without Codelink attached to the simulation are identical.
What You Will Learn
- How Codelink accelerates the diagnostic and debug phase of your processor-based design using processor-driven tests
- Benefits for a processor-driven verification methodology
About the Presenter
Marc Bryan
Marc Bryan has been both a leading and contributing member of tool development teams for more than 24 years. Currently serving as the Product Marketing Manager for Mentor Graphics’ Codelink products, Bryan comes to Mentor after 5 and a half years with ARM’s tool division, where he managed system-level model and debug products for single and multi-core processor-based designs. A prior hands-on role at Korg R&D provided extensive embedded processor-based, system-level design and implementation experience.
Who Should View
- HW Verification Engineers of ARM, MIPS, or IBM PowerPC processor-based designs
Related Resources
Multimedia
Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs
ARM is leading the industry in multi-core design with its Cortex™-A series applications processors including both its high-performance ARM Cortex™-A15 and its high-efficiency ARM Cortex-A7....…View On-demand Web Seminar
Verifying Complex SoC Designs with Questa Codelink
This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments.…View On-demand Web Seminar
Effective SoC Verification: The Hardware and Software Challenge
How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized...…View Technology Overview
Other Related Resources
To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?
White Paper: With power becoming a critical design constraint in the design environment, designers are utilizing advanced techniques to minimize power consumption in their designs. As a result, the RTL design is being...…View White Paper
Advanced Verification of Low Power Designs
White Paper: Power consumption due to leakage has become a major factor in the total power consumption equation for battery powered and sub-100 nm designs, compelling design teams to adopt various power management design...…View White Paper
Functional Verification of Low Power Designs at RTL
White Paper: Power is the number one constraint impacting today’s electronic designs. The need to minimize dynamic and static power consumption creates unique verification challenges. A common low power design...…View White Paper