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Easier Debug of Processor-Based Designs

Details

Overview

  • Do you have one or more CPU's in your current project?
  • Are you running software to test your hardware integration?
  • Have you ever turned your CPU cache off or added printf statements to your code just to figure out why your test is failing?
  • Have you ever crossed your fingers prior to running your non-regression test overnight hoping you don’t have to debug the next day?

With increasing numbers of CPU cores required in each new design generation, leveraging their capabilities by running software to verify the hardware is common practice. However, the task of debugging software by simply looking into the hardware debugger, as in the old days with the 8051 single 8bits bus processor, can get very tedious when a test fails and you need to find out why!

During this presentation we will show how to efficiently debug software and hardware together by providing a solution which avoids launching simulation time and time again to figure out what went wrong.

What You Will Learn

  • How to take advantage of your CPU to test your hardware
  • Useful debug environment to debug SW and HW together
  • New techniques to spend less time debugging

Who Should View

  • Verification engineers verifying SoC with one or more CPU’s
  • Verification engineers running Software to test their Hardware
  • Software engineers developing low level drivers
  • Technical Managers
  • Anyone debugging simulation running HW and SW together
  • Technical managers looking for ways of improving their bug catching rate

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