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Showing: 13-24 of 87
Configuration in UVM

Configuration in UVM

30:17

On-demand Web Seminar: 30:17

Tags: UVM, UVM Recipe of the Month, Verification Academy

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More UVM Registers

More UVM Registers

42:11

On-demand Web Seminar: The inclusion of the Register Layer was one of the most requested features of UVM. This session will expand on the introductory session delivered in October to discuss how to implement registers and also... 42:11

Tags: Registers, UVM, UVM Recipe of the Month, Verification Academy

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Questa CDC Verification Demo

Questa CDC Verification Demo

10:08

Product Demo: This is a demo of Mentor's CDC verification solution. During the demonstration we will show you why Mentor is a leader in CDC verification and how our solution will help you find bugs missed by all other... 10:08

Tags: CDC, Clock-Domain Crossing, Questa® CDC Verification

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Sequence Layering

Sequence Layering

01:01:43

On-demand Web Seminar: Many protocols have a hierarchical definition, and sometimes we may want to create a protocol-independent layer on top of a standard protocol to support the development of protocol-independent components... 01:01:43

Tags: Layering, Sequence, UVM, UVM Recipe of the Month, Verification Academy

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Advanced Technology for Advanced Verification,Advanced Technology for Block Level

Advanced Technology for Advanced Verification,Advanced Technology for Block Level

42:40

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Re-defining Verification Performance

Re-defining Verification Performance

39:00

Technology Overview:  Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's... 39:00

Tags: Verification Management

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Effective SoC Verification: The Hardware and Software Challenge

Effective SoC Verification: The Hardware and Software Challenge

25:50

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Solutions Expo Keynote:

Solutions Expo Keynote:

39:14

Technology Overview: Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's Law.... 39:14

Tags: OVM, Questa® inFact

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Equivalence Check Satisfies Safety Verification IEC61508 for Robotics

Equivalence Check Satisfies Safety Verification IEC61508 for Robotics

16:22

Technology Overview: In this session, Jim Henson, Product Marketing Manager at Mentor Graphics discusses IEC 61508, "Functional safety of electrical/electronic/programmable electronic safety-related systems." This... 16:22

Tags: FormalPro

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Questa inFact: Verifying a DMA Controller

Questa inFact: Verifying a DMA Controller

17:05

Technology Overview: Questa inFact is a stimulus-generation tool that accelerates functional coverage closure. In this demo, you will see how Questa inFact is applied to verification of a DMA controller. The key features of... 17:05

Tags: Questa® inFact

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Make Functional Verification your Competitive Differentiator

Make Functional Verification your Competitive Differentiator

37:49

Technology Overview: Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of... 37:49

Tags: Codelink, Questa® Advanced Simulator, Questa® inFact

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Clock Domain Crossing Verification

Clock Domain Crossing Verification

15:17

Technology Overview: Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between... 15:17

Tags: Questa® CDC Verification

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Showing: 13-24 of 87
 
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