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Showing: 73-84 of 88
Simulating the RTL and Running Code Coverage

Simulating the RTL and Running Code Coverage

27:17

Technology Overview: Simulation is part of design verification, a DO-254 supporting process that ensures that the device successfully meets requirements. Simulation tests are typically run throughout the DO-254 design flow... 27:17

Tags: ModelSim®

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Simulating the Gate-Level Netlist with Timing

Simulating the Gate-Level Netlist with Timing

14:11

Technology Overview: Gate-level simulation verifies the output of the synthesis and place & route tools and incorporates timing to bring the model closer to real implementation. It ensures that a device will perform precisely... 14:11

Tags: ModelSim®

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Using Logical Equivalency Checking to Verify the Netllist

Using Logical Equivalency Checking to Verify the Netllist

29:43

Technology Overview: A logic equivalency checking (LEC) verification process supports DO-254 compliance and helps reduce dependence on gate-level simulation for complex FPGA projects. In this video, DO-254 program manager Michelle... 29:43

Tags: FormalPro

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Assertion-Based Verification for a DO-254 Program

Assertion-Based Verification for a DO-254 Program

27:09

Technology Overview: Assertion-based verification (ABV) is a more modern approach to verification that can also validate the requirements phase of a DO-254 program. In this video, DO-254 program manager Michelle Lange shows... 27:09

Tags: Questa® Advanced Simulator

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Why is OVM and Hardware Acceleration Such a Viable Solution

Why is OVM and Hardware Acceleration Such a Viable Solution

25:56

On-demand Web Seminar: OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system... 25:56

Tags: OVM, Questa® Advanced Simulator

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Verification Strategy for Mixed-Signal SoCs

Verification Strategy for Mixed-Signal SoCs

30:21

On-demand Web Seminar: This Technical discussion will look into various tools available for Analog design verification, help understand underlying techniques and how they fit into SoC verification and how to take advantage of... 30:21

Tags: Analog Mixed-Signal, Questa® ADMS

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How do you determine the right way to improve your verification capability?

How do you determine the right way to improve your verification capability?

14:59

Technology Overview: Whatever you are designing, verification is becoming an increasingly complex and time consuming activity. Determining how best to improve your verification capability can seem almost as difficult doing... 14:59

Tags: Questa® Advanced Simulator

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Questa: SystemVerilog Verification from Requirements to Coverage Closure

Questa: SystemVerilog Verification from Requirements to Coverage Closure

35:54

Technology Overview: SystemVerilog delivers advanced functional verification techniques in an industry standard language. However, the effective, predictable verification of electronic systems takes much more than constrained-random... 35:54

Tags: Questa® Advanced Simulator

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Verification Planning and Management Consulting

Verification Planning and Management Consulting

Technology Overview: Author and Senior Mentor Consultant Peet James presents a sample of our solution in this Verification Planning & Management Module. Mr. James explains how to transform the typically open-ended verification...

Tags: Verification Management

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What is “Intelligent Testbench Automation”?

What is “Intelligent Testbench Automation”?

40:39

On-demand Web Seminar: Discuss the methods behind Mentor’s intelligent testbench automation tool, Questa inFact. It will present how to apply different verification strategies without having to re-write the entire test... 40:39

Tags: Questa® inFact, Testbench Automation

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Easier Debug of Processor-Based Designs

Easier Debug of Processor-Based Designs

28:59

On-demand Web Seminar: During this presentation we will show how to efficiently debug software and hardware together by providing a solution which avoids launching simulation time and time again to figure out what went wrong. 28:59

Tags: Codelink, Processor Driven Verification

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Improving Visibility & Efficiency with Verification Management

Improving Visibility & Efficiency with Verification Management

48:55

Technology Overview: Verification management is one of the most important factors in today’s verification of silicon chips and SoC designs. Every development team manages their verification process in some way, but how... 48:55

Tags: Questa® Advanced Simulator, Verification Management

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Showing: 73-84 of 88
 
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