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Featured Multimedia
Advanced UVM Debugging
47:58On-demand Web Seminar: This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2. 47:58
Tags: Debugging, Questa Codelink, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification IP, Questa Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, UVM
The 2012 Wilson Research Group Functional Verification Study
39:15On-demand Web Seminar: Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world. In this presentation, Harry Foster... 39:15
Tags: ModelSim®, Questa ADMS, Questa Codelink, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification IP, Questa Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, Wilson Research Group Study
Cookbook Recipes Beyond UVM: Effectively Modeling and Analyzing Coverage
42:28On-demand Web Seminar: 42:28
Tags: Modeling, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification IP, Questa Verification Management, Questa® Advanced Simulator, UVM
OVM to UVM Migration
58:14On-demand Web Seminar: A step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features... 58:14
Tags: OVM, Questa® Advanced Simulator, UVM, UVM Recipe of the Month, Verification Academy Cookbook
Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL
42:48On-demand Web Seminar: This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced... 42:48
Tags: Debug, OVM, Questa® Advanced Simulator, testbench, UVM
Advanced Debug with Questa
01:22:23On-demand Web Seminar: Debug Verilog deltas, process debugging, tracing through source code, comparing results of waveform files, vcd stimulus. Whatever your debugging requirements, this comprehensive technical debug seminar... 01:22:23
Tags: Debug, Questa® Advanced Simulator
ModelSim to Questa Core: Adopting Assertion-Based Verification to Improve Your FPGA Debug and Design Quality
48:23On-demand Web Seminar: Learn how Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL). 48:23
Tags: Assertion-Based Verification, Debug, ModelSim®, Questa® Advanced Simulator
Why is OVM and Hardware Acceleration Such a Viable Solution
25:56On-demand Web Seminar: OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system... 25:56
Tags: OVM, Questa® Advanced Simulator
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