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Multimedia Resource Center

Showing: 1-5 of 5
Advanced UVM Debugging

Advanced UVM Debugging

47:58

On-demand Web Seminar: This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2. 47:58

Tags: Codelink, Debugging, Questa® CoverCheck, Questa® Power Aware Simulator, Questa® Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, UVM, UVM Recipe of the Month, Verification Academy

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The 2012 Wilson Research Group Functional Verification Study

The 2012 Wilson Research Group Functional Verification Study

39:15

On-demand Web Seminar: Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster... 39:15

Tags: Codelink, ModelSim®, Questa® ADMS, Questa® CoverCheck, Questa® Power Aware Simulator, Questa® Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, Wilson Research Group Study

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Industrial-Strength Clock Domain Crossing Verification

Industrial-Strength Clock Domain Crossing Verification

27:20

On-demand Web Seminar: More than 90% of today’s designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. This webinar presents Questa... 27:20

Tags: Questa® CDC Verification, Questa® Formal Verification

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Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar

Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar

26:52

On-demand Web Seminar: This webinar focuses on the how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior. We show through a set of detailed examples how non-determinism caused... 26:52

Tags: CDC, Debug, Questa® CDC Verification

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Clock-Domain Crossing Verification for FPGAs

Clock-Domain Crossing Verification for FPGAs

46:02

On-demand Web Seminar: Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as ASIC designers are. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming... 46:02

Tags: CDC, Questa® CDC Verification

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