Multimedia Resource Center

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management

Technology Overview: The final stage of DO-254 verification and validation, hardware testing examines the performance of the device in its operational environment. DO-254 program manager Michelle Lange explains how a suite... 10:10

Tags: ModelSim®, Questa® Advanced Simulator, Questa® CDC Verification, SystemVision

Technology Overview: Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between... 15:17

Tags: Questa® CDC Verification

Technology Overview: The drive to smaller, more efficient devices increases the risk of metastability in multi-clock designs, causing subtle problems that are difficult to debug with traditional verification techniques. They... 23:08

Tags: Questa® CDC Verification