Multimedia Resource Center

On-demand Web Seminar: This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2. 47:58

Tags: Debugging, Questa Codelink, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification IP, Questa Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, UVM

On-demand Web Seminar: Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster... 39:15

Tags: ModelSim®, Questa ADMS, Questa Codelink, Questa CoverCheck, Questa Power Aware Simulator, Questa Verification IP, Questa Verification Management, Questa® Advanced Simulator, Questa® CDC Verification, Questa® Formal Verification, Questa® inFact, Wilson Research Group Study

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management