Multimedia Resource Center

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Questa Codelink, Questa® CDC Verification, Verification Management

Technology Overview: Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of... 37:49

Tags: Questa Codelink, Questa® Advanced Simulator, Questa® inFact

Technology Overview: Using a full-functional processor model to drive bus-cycles into a block or chip level simulation is a powerful method to verify SoC designs. Since the end product is processor driven, this “real... 14:13

Tags: Processor Driven Verification, Questa Codelink