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Showing: 49-60 of 87

Power Aware Verification


On-demand Web Seminar: Power aware verification checks that the planned active power management architecture and controls will operate correctly and will enable the design to operate correctly as the design transitions from one... 23:12

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ModelSim to Questa Core: Adopting Assertion-Based Verification to Improve Your FPGA Debug and Design Quality


On-demand Web Seminar: Learn how Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL). 47:35

Tags: Assertion-Based Verification, Debug, ModelSim®, Questa® Advanced Simulator

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Clock-Domain Crossing Verification for FPGAs


On-demand Web Seminar: Today FPGA designers are equally plagued by clock-domain crossing (CDC) problems as ASIC designers are. Simulation alone doesn't catch the CDC bugs, resulting in an extremely difficult and time-consuming... 46:02

Tags: CDC, Questa® CDC Verification

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Off-line Debug of Multi-Core SoCs with Veloce Emulation


On-demand Web Seminar: Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design... 32:04

Tags: Codelink, Emulation, SoC Verification

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Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs


On-demand Web Seminar: ARM is leading the industry in multi-core design with its Cortex™-A series applications processors including both its high-performance ARM Cortex™-A15 and its high-efficiency ARM Cortex-A7.... 35:48

Tags: ARM, Codelink, SoC

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Dennis Brophy at DAC 2012


Technology Overview: Interview with Mentor Graphics' Dennis Brophy at DAC 2012. 05:01

Tags: DAC, Questa® Formal Verification

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John Lenyo at DAC 2012


Technology Overview: Interview with Mentor Graphics' John Lenyo at DAC 2012. 09:08

Tags: DAC, Questa® Formal Verification

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Harry Foster at DAC 2012


Technology Overview: Interview with Mentor Graphics' Harry Foster at DAC 2012. 08:34

Tags: DAC, Questa® Formal Verification

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Verifying Complex SoC Designs with Questa Codelink


On-demand Web Seminar: This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments. 33:38

Tags: Codelink, Debug, SoC

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Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL


On-demand Web Seminar: This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced... 42:48

Tags: Debug, OVM, Questa® Advanced Simulator, testbench, UVM

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Functional Verification - Volume To Velocity - Tech Design Forum


Technology Overview: Keynote Tech Design Forum Israel 2011: "From Volume to Velocity", presented by Stephen Bailey, Director of Marketing at Mentor Graphics. 47:12

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ESL Simulation with Veloce Hardware Emulation


On-demand Web Seminar: This session presents an overview of the Veloce emulator and its integration with Vista. 26:58

Tags: Vista

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Showing: 49-60 of 87
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