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Showing: 1-11 of 11

Featured Multimedia

Advanced UVM Debugging

Advanced UVM Debugging

47:58

On-demand Web Seminar: This web seminar will highlight some new strategies for debugging UVM-based testbenches using Questa 10.2. 47:58

Tags: Codelink, Debugging, Questa® Advanced Simulator, Questa® CDC Verification, Questa® CoverCheck, Questa® Formal Verification, Questa® inFact, Questa® Power Aware Simulator, Questa® Verification Management, UVM, UVM Recipe of the Month, Verification Academy

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Advanced Technology for Advanced Verification,Advanced Technology for Block Level

Advanced Technology for Advanced Verification,Advanced Technology for Block Level

42:40

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Effective SoC Verification: The Hardware and Software Challenge

Effective SoC Verification: The Hardware and Software Challenge

25:50

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Make Functional Verification your Competitive Differentiator

Make Functional Verification your Competitive Differentiator

37:49

Technology Overview: Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of... 37:49

Tags: Codelink, Questa® Advanced Simulator, Questa® inFact

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The 2012 Wilson Research Group Functional Verification Study

The 2012 Wilson Research Group Functional Verification Study

39:15

On-demand Web Seminar: Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster... 39:15

Tags: Codelink, ModelSim, Questa® ADMS, Questa® Advanced Simulator, Questa® CDC Verification, Questa® CoverCheck, Questa® Formal Verification, Questa® inFact, Questa® Power Aware Simulator, Questa® Verification Management, Wilson Research Group Study

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Off-line Debug of Multi-Core SoCs with Veloce Emulation

Off-line Debug of Multi-Core SoCs with Veloce Emulation

32:04

On-demand Web Seminar: Today’s multi-core system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers, that force users to closely integrate software development and validation with silicon design... 32:04

Tags: Codelink, Emulation, SoC Verification

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Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs

Making Hardware/Software Co-Verification Easier for ARM Cortex™-A Series Processor-based Designs

35:48

On-demand Web Seminar: ARM is leading the industry in multi-core design with its Cortex™-A series applications processors including both its high-performance ARM Cortex™-A15 and its high-efficiency ARM Cortex-A7.... 35:48

Tags: ARM, Codelink, SoC

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Verifying Complex SoC Designs with Questa Codelink

Verifying Complex SoC Designs with Questa Codelink

33:38

On-demand Web Seminar: This session shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments. 33:38

Tags: Codelink, Debug, SoC

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Easily Inspect & Find Defects in Your Processor-Based Design and Testbench

Easily Inspect & Find Defects in Your Processor-Based Design and Testbench

31:27

On-demand Web Seminar: If you are running processor-driven tests with hundreds of thousands of lines of test code in digital simulation on your processor-based design, you know how difficult and time-consuming it is to figure... 31:27

Tags: Codelink, Processor Driven Verification

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Easier Debug of Processor-Based Designs

Easier Debug of Processor-Based Designs

28:59

On-demand Web Seminar: During this presentation we will show how to efficiently debug software and hardware together by providing a solution which avoids launching simulation time and time again to figure out what went wrong. 28:59

Tags: Codelink, Processor Driven Verification

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Processor Driven Verification

Processor Driven Verification

14:13

Technology Overview: Using a full-functional processor model to drive bus-cycles into a block or chip level simulation is a powerful method to verify SoC designs. Since the end product is processor driven, this “real... 14:13

Tags: Codelink, Processor Driven Verification

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