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Multimedia Resource Center

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Featured Multimedia

Veloce Speeds Debug of Ostendo Mobile 3D Projector on Chip

02:08

Technology Overview: Phuong-Anh, Sr. ASIC Verification Engineer at Ostendo Technologies Inc. describes how the Veloce emulator’s ability to run extensive, long tests allowed them to run many iterations of their firmware... 02:08

Tags: Veloce2, Verification Management

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Advanced Technology for Advanced Verification,Advanced Technology for Block Level

42:40

Technology Overview: Although constrained random stimulus generation is an automated way to achieve coverage of your design’s functionality during simulation, it is now possible to achieve even higher coverage, faster.... 42:40

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Re-defining Verification Performance

39:00

Technology Overview:  Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's... 39:00

Tags: Verification Management

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Effective SoC Verification: The Hardware and Software Challenge

25:50

Technology Overview: How do you achieve full-chip verification while meeting your project schedule and quality metrics? Your team’s goal is to verify a SoC consisting of an embedded CPU(s), bus fabric, and multiple specialized... 25:50

Tags: Certe Testbench Studio, Codelink, Questa® CDC Verification, Verification Management

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Solutions Expo Keynote:

39:14

Technology Overview: Performance is key to achieving verification productivity. Yet, traditional brute force approaches to improving performance will only provide incremental benefits, which will not keep up with Moore's Law.... 39:14

Tags: OVM, Questa® inFact

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Equivalence Check Satisfies Safety Verification IEC61508 for Robotics

16:22

Technology Overview: In this session, Jim Henson, Product Marketing Manager at Mentor Graphics discusses IEC 61508, "Functional safety of electrical/electronic/programmable electronic safety-related systems." This... 16:22

Tags: FormalPro

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Questa inFact: Verifying a DMA Controller

17:05

Technology Overview: Questa inFact is a stimulus-generation tool that accelerates functional coverage closure. In this demo, you will see how Questa inFact is applied to verification of a DMA controller. The key features of... 17:05

Tags: Questa® inFact

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Make Functional Verification your Competitive Differentiator

37:49

Technology Overview: Companies that master the functional verification challenges for today's chips have a competitive advantage in that they can get products to market faster. In this keynote we identify the core pieces of... 37:49

Tags: Codelink, Questa® Advanced Simulator, Questa® inFact

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Clock Domain Crossing Verification

15:17

Technology Overview: Most ASIC and FPGA designs on the drawing board today have multiple asynchronous clocks. With traditional simulation and static timing based methodologies coming up short in verifying the interaction between... 15:17

Tags: Questa® CDC Verification

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Dennis Brophy at DAC 2012

05:01

Technology Overview: Interview with Mentor Graphics' Dennis Brophy at DAC 2012. 05:01

Tags: DAC, Questa® Formal Verification

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John Lenyo at DAC 2012

09:08

Technology Overview: Interview with Mentor Graphics' John Lenyo at DAC 2012. 09:08

Tags: DAC, Questa® Formal Verification

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Harry Foster at DAC 2012

08:34

Technology Overview: Interview with Mentor Graphics' Harry Foster at DAC 2012. 08:34

Tags: DAC, Questa® Formal Verification

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