Multimedia Resource Center
Delivering 10X Design Improvements
44:00Technology Overview: Time and time again, escalating complexity has threatened to derail the IC industry from the extraordinary 35% annual reduction in transistor pricing it has enjoyed the past 40+ years. Fortunately, in... 44:00
Debug Productivity with Questa: Introduction to advanced debug features in Questa for SystemVerilog class-based TB, OVM/UVM, and hard to find problems in RTL
42:48On-demand Web Seminar: This webinar will introduce the advanced debug capabilities available in Questa for class-based debug of OOP environments with SystemVerilog, OVM, UVM and SystemC, Assertion debug with SVA or PSL and advanced... 42:48
Tags: Debug, OVM, Questa® Advanced Simulator, testbench, UVM
Questa Formal's AutoCheck - The Push-Button Way to Find Bugs
35:10On-demand Web Seminar: The Autocheck feature of the Questa Formal Verification tool from Mentor Graphics allows designers and verification engineers to quickly and easily verify that a design is free of many common functional... 35:10
Tags: automatic formal check, Questa® Formal Verification
Industrial-Strength Clock Domain Crossing Verification
27:20On-demand Web Seminar: More than 90% of today’s designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. This webinar presents Questa... 27:20
Tags: Questa® CDC Verification, Questa® Formal Verification
The Verification Academy - A Roadmap to Advanced Functional Verification Adoption
52:40On-demand Web Seminar: The Verification Academy is the first of its kind. Its goals are simple: to provide you everything necessary to advance your skills and evolve your organization's advanced functional verification capabilities... 52:40
Tags: OVM, UVM, Verification Academy
Questa CDC - Verifying CDC Reconvergence with Silicon-Accurate Models Webinar
26:52On-demand Web Seminar: This webinar focuses on the how to ensure that simulations of such designs can nevertheless be accurate predictors of silicon behavior. We show through a set of detailed examples how non-determinism caused... 26:52
Tags: CDC, Debug, Questa® CDC Verification
Using ModelSim to Improve Simulation Runtime and Debug Productivity
25:25On-demand Web Seminar: This comprehensive technical webinar will show you how to improve time-to-market for complex SoC designs through reduced simulation runtime and process debugs, thanks to Mentor Graphics ModelSim’s... 25:25
Tags: Debug, ModelSim®
Advanced Debug with Questa
01:22:23On-demand Web Seminar: Debug Verilog deltas, process debugging, tracing through source code, comparing results of waveform files, vcd stimulus. Whatever your debugging requirements, this comprehensive technical debug seminar... 01:22:23
Tags: Debug, Questa® Advanced Simulator
Active Power Management Verification with Power Aware Simulation
36:48On-demand Web Seminar: Power management has become a critical aspect of electronic systems design. Driven by customer demand for more functionality and longer battery life in portable electronics, and enabled by advances... 36:48
Tags: Low Power, Questa Power Aware Simulator, UPF
Improving Quality and Time-to-Market with Formal Verification
44:16On-demand Web Seminar: This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic... 44:16
Tags: Assertion-Based Verification, Formal Verification, Questa® Formal Verification
Leveraging Questa Verification IP to Achieve More Verification with Less Effort
20:25On-demand Web Seminar: Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today. Many tools and techniques exist to help with this problem including languages, verification methodologies... 20:25
Tags: Questa Verification IP, SoC Verification
Power Aware Verification
23:12On-demand Web Seminar: Power aware verification checks that the planned active power management architecture and controls will operate correctly and will enable the design to operate correctly as the design transitions from one... 23:12
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