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Accelerating Coverage Closure with Intelligent Testbench Automation

Accelerating Coverage Closure with Intelligent Testbench Automation

24:58

On-demand Web Seminar: The Questa Questa inFact Intelligent Testbench Automation solution generates stimulus according to the user s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases.... 24:58

Tags: Questa® inFact

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Developing the Conceptual Design

Developing the Conceptual Design

04:12

Technology Overview: The DO-254 process defines conceptual design as a "high-level design concept that may be assessed to determine the potential for the resulting design implementation to meet the requirements." In... 04:12

Tags: Vista, Vista

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Understanding CDC Analysis for a DO-254 Program

Understanding CDC Analysis for a DO-254 Program

23:08

Technology Overview: The drive to smaller, more efficient devices increases the risk of metastability in multi-clock designs, causing subtle problems that are difficult to debug with traditional verification techniques. They... 23:08

Tags: Questa® CDC Verification

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Simulating the RTL and Running Code Coverage

Simulating the RTL and Running Code Coverage

27:17

Technology Overview: Simulation is part of design verification, a DO-254 supporting process that ensures that the device successfully meets requirements. Simulation tests are typically run throughout the DO-254 design flow... 27:17

Tags: ModelSim®

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Simulating the Gate-Level Netlist with Timing

Simulating the Gate-Level Netlist with Timing

14:11

Technology Overview: Gate-level simulation verifies the output of the synthesis and place & route tools and incorporates timing to bring the model closer to real implementation. It ensures that a device will perform precisely... 14:11

Tags: ModelSim®

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Using Logical Equivalency Checking to Verify the Netllist

Using Logical Equivalency Checking to Verify the Netllist

29:43

Technology Overview: A logic equivalency checking (LEC) verification process supports DO-254 compliance and helps reduce dependence on gate-level simulation for complex FPGA projects. In this video, DO-254 program manager Michelle... 29:43

Tags: FormalPro

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Assertion-Based Verification for a DO-254 Program

Assertion-Based Verification for a DO-254 Program

27:09

Technology Overview: Assertion-based verification (ABV) is a more modern approach to verification that can also validate the requirements phase of a DO-254 program. In this video, DO-254 program manager Michelle Lange shows... 27:09

Tags: Questa® Advanced Simulator

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Why is OVM and Hardware Acceleration Such a Viable Solution

Why is OVM and Hardware Acceleration Such a Viable Solution

25:56

On-demand Web Seminar: OVM promotes the use of untimed transaction-based testbenches for simulation and such an approach can be complimentary with hardware acceleration for both high performance and effective creation of system... 25:56

Tags: OVM, Questa® Advanced Simulator

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Verification Strategy for Mixed-Signal SoCs

Verification Strategy for Mixed-Signal SoCs

30:21

On-demand Web Seminar: This Technical discussion will look into various tools available for Analog design verification, help understand underlying techniques and how they fit into SoC verification and how to take advantage of... 30:21

Tags: Analog Mixed-Signal, Questa ADMS

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How do you determine the right way to improve your verification capability?

How do you determine the right way to improve your verification capability?

14:59

Technology Overview: Whatever you are designing, verification is becoming an increasingly complex and time consuming activity. Determining how best to improve your verification capability can seem almost as difficult doing... 14:59

Tags: Questa® Advanced Simulator

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Questa: SystemVerilog Verification from Requirements to Coverage Closure

Questa: SystemVerilog Verification from Requirements to Coverage Closure

35:54

Technology Overview: SystemVerilog delivers advanced functional verification techniques in an industry standard language. However, the effective, predictable verification of electronic systems takes much more than constrained-random... 35:54

Tags: Questa® Advanced Simulator

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Using Code Coverage with ModelSim

Using Code Coverage with ModelSim

60:00

On-demand Web Seminar: With today's complex SoCs, the time spent on verification now consumes 70 percent of the total development time. A more efficient and effective verification methodology is crucial for improving first pass... 60:00

Tags: ModelSim®

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Showing: 61-72 of 80