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Verification Planning and Management Consulting

Verification Planning and Management Consulting

Technology Overview: Author and Senior Mentor Consultant Peet James presents a sample of our solution in this Verification Planning & Management Module. Mr. James explains how to transform the typically open-ended verification...

Tags: Verification Management

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What is “Intelligent Testbench Automation”?

What is “Intelligent Testbench Automation”?

40:39

On-demand Web Seminar: Discuss the methods behind Mentor’s intelligent testbench automation tool, Questa inFact. It will present how to apply different verification strategies without having to re-write the entire test... 40:39

Tags: Questa® inFact, Testbench Automation

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Easier Debug of Processor-Based Designs

Easier Debug of Processor-Based Designs

28:59

On-demand Web Seminar: During this presentation we will show how to efficiently debug software and hardware together by providing a solution which avoids launching simulation time and time again to figure out what went wrong. 28:59

Tags: Processor Driven Verification, Questa Codelink

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Improving Visibility & Efficiency with Verification Management

Improving Visibility & Efficiency with Verification Management

48:55

Technology Overview: Verification management is one of the most important factors in today’s verification of silicon chips and SoC designs. Every development team manages their verification process in some way, but how... 48:55

Tags: Questa® Advanced Simulator, Verification Management

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OVM: The Open Verification Methodology

OVM: The Open Verification Methodology

26:39

Technology Overview: This session covers the use and benefits of the Open Verification Methodology (OVM). The OVM brings together verification knowledge, experience and expertise to provide an approach to building verification... 26:39

Tags: OVM, Questa® Advanced Simulator

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Processor Driven Verification

Processor Driven Verification

14:13

Technology Overview: Using a full-functional processor model to drive bus-cycles into a block or chip level simulation is a powerful method to verify SoC designs. Since the end product is processor driven, this “real... 14:13

Tags: Processor Driven Verification, Questa Codelink

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Questa inFact Intelligent Testbench Automation

Questa inFact Intelligent Testbench Automation

16:47

Technology Overview: When asked about the state of functional verification, Gary Smith, founder and chief analyst for market research company Gary Smith EDA, commented, “Throwing engineers at the problem is not an acceptable... 16:47

Tags: Questa® Advanced Simulator, Questa® inFact, Testbench Automation

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Showing: 73-80 of 80