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FPGA Verification Automation with Mentor VIP



Verification of IP blocks, subsystems and complete SOCs is a major challenge for the industry today.  Verification teams are using multiple tools and methodologies to achieve design functionality. One very common and valuable tool is Verification IP. Mentor Graphics VIP provides comprehensive protocol test stimulus and coverage checking that allows you to easily deploy advanced verification methodologies. Verification planning, constrained random and functional coverage methodologies are all included for standard bus protocols, in this case PCIe. 

This webinar will focus on PCIe which is one of the most commonly used protocols and also one of the most complicated.

What You Will Learn

  • Learn how Mentor VIP is the best solution for difficult verification tasks
  • Learn why Mentor VIP is the easiest solution for adopting verification automation for any FPGA team with standard protocols

About the Presenter

Presenter Image Joe Rodriguez

Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.

Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.

Who Should View

  • Verification Engineers and Managers

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