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Improving Quality and Time-to-Market with Formal Verification



This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic checks enable designers to easily qualify code before check-in, without assertions or constraints.

Formal applications use assertion generation and formal verification to quickly and thoroughly verify specific design requirements or tool assumptions that would otherwise be tedious and time-consuming to address. Assertion-based verification enables verification of critical functionality such as control logic to ensure that failures cannot occur. Post-silicon debug using formal verification makes it possible to quickly discover the root cause of an observed failure and confirm that a proposed fix is correct.

The webinar will provide a detailed overview of these capabilities of Questa Formal Verification and the value they bring to functional verification.

What You Will Learn

  • Automatic Checks
  • Formal Applications
  • Assertion-Based Verification
  • Post-Silicon Debug

About the Presenter

Presenter Image Mark Eslinger

Mr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.

Who Should View

  • Design/Verification Engineers
  • Design/Verification Managers
  • Project Managers
  • CAD/Methodology Managers

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