Improving Quality and Time-to-Market with Formal Verification
Requires Flash Player.
This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic checks enable designers to easily qualify code before check-in, without assertions or constraints. Formal applications use assertion generation and formal verification to quickly and thoroughly verify specific design requirements or tool assumptions that would otherwise be tedious and time-consuming to address. Assertion-based verification enables verification of critical functionality such as control logic to ensure that failures cannot occur. Post-silicon debug using formal verification makes it possible to quickly discover the root cause of an observed failure and confirm that a proposed fix is correct. The webinar will provide a detailed overview of these capabilities of Questa Formal Verification and the value they bring to functional verification.
Duration: 44:16
Tags: Assertion-Based Verification, Questa® Formal Verification
View On-demand Web Seminar (Opens in New Window/External URL)
Details
Overview
This webinar presents Questa Formal Verification and explains how it is being used today, by both designers and verification engineers, to improve design quality and accelerate verification. Automatic checks enable designers to easily qualify code before check-in, without assertions or constraints.
Formal applications use assertion generation and formal verification to quickly and thoroughly verify specific design requirements or tool assumptions that would otherwise be tedious and time-consuming to address. Assertion-based verification enables verification of critical functionality such as control logic to ensure that failures cannot occur. Post-silicon debug using formal verification makes it possible to quickly discover the root cause of an observed failure and confirm that a proposed fix is correct.
The webinar will provide a detailed overview of these capabilities of Questa Formal Verification and the value they bring to functional verification.
What You Will Learn
- Automatic Checks
- Formal Applications
- Assertion-Based Verification
- Post-Silicon Debug
About the Presenter
Mark Eslinger
Mr. Eslinger has over 20 years of experience in chip design & verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics Mr Eslinger has a special focus on assertion-based methods and formal verification. In this role he works with customers worldwide to help them adopting advanced methodologies. Prior to Mentor Mr. Eslinger has held positions in the engineering and technical marketing organizations in the semiconductor, systems and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. Mr Eslinger holds a MSEE from Santa Clara University.
Who Should View
- Design/Verification Engineers
- Design/Verification Managers
- Project Managers
- CAD/Methodology Managers
Related Resources
Multimedia
Questa Formal's AutoCheck - The Push-Button Way to Find Bugs
The Autocheck feature of the Questa Formal Verification tool from Mentor Graphics allows designers and verification engineers to quickly and easily verify that a design is free of many common functional...…View On-demand Web Seminar
Industrial-Strength Clock Domain Crossing Verification
More than 90% of today’s designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. This webinar presents Questa...…View On-demand Web Seminar
Advanced Formal Verification
In recent years, formal verification has emerged as an alternative approach that addresses the main limitation of simulation-based verification: checking a small fraction of the behaviours of non-trivial...…View On-demand Web Seminar
Other Related Resources
Using Formal Verification to Check SoC Connectivity Correctness
White Paper: Formal verification offers a solution that is quick, exhaustive and allows for efficient debug. It’s true that traditionally, chip-level formal verification is impractical. The approach usually targets...…View White Paper
Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper
Static and Formal Verification of Power Aware Designs at the RTL Using UPF
White Paper: The Unified Power Format (UPF) low power specification standard allows designers to explicitly specify the insertion of isolation cells and level shifters at the RTL. In this paper, Rudra Mukherjee and...…View White Paper