Injecting Automation into Verification – Improved Throughput
On-demand Web Seminar
This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system. We will also describe common techniques for improving simulation performance. If you are able to stimulate your design with simulation more effectively you will find that debug productivity in simulation is vastly superior to debug time in an hardware lab. We will show common and recent improvements in simulation debug throughput. We also highlight additional pre-built verification automation components for verification process throughput.
What You Will Learn
- Learn how make writing tests easier
- Learn how deploy an optimized simulation model
- Learn latest techniques for root cause analysis
- Learn how standard protocols are an opportunity for verification automation
About the Presenter
Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.
Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.
Who Should View
- Design Engineers
- Verification Engineers
- Quality Engineers
UVM Sequences in Depth
In this webinar, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt...…
Injecting Automation into Verification - FPGA Market Trends
This webinar provides a management perspective into FPGA market trends and the high value solutions targeted at common design verification tasks.…
Other Related Resources
UVM: The Next Generation in Verification Methodology
White Paper: UVM is a new verification methodology that was developed by the verification community for the verification community. UVM represents the latest advancements in verification technology and is designed to...…
OVM to UVM Transition
Training Course: This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the...…