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What is “Intelligent Testbench Automation”?



Since the phrase “Verification Bottleneck” was first reported, EDA companies have brought to market many verification tools to automate different aspects of the verification challenge. Amongst them are intelligent testbench automation solutions.

The aim of intelligent testbench automation is to find more design bugs earlier in the verification process. In doing so this technology accelerates functional coverage closure by at least an order of magnitude compared to traditional constrained random testbenches.

This webinar will discuss the methods behind Mentor’s intelligent testbench automation tool, Questa inFact.  It will present how to apply different verification strategies without having to re-write the entire test bench and how intelligent testbench components fit into your overall verification architecture.

What You Will Learn

  • How to minimize the “time-to-next-bug”
  • How to reach your functional coverage goals – within a predictable timeline
  • How to create test benches that can adapt to different verification strategies – without the need for massive re-writes

Who Should View

  • Verification engineers using traditional HVL’s (Vera, ‘e’..) to verify hardware designs
  • Design engineers struggling to create effective test benches in VHDL or Verilog
  • Design and verification managers trying to manage more complex design projects with less resources and time

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