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Mentor VIP, More than just a BFM



Today’s advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc.  For UVM environment infrastructure Questa VIP supports the operating modes required for block to top environment reuse as well as transaction monitoring and capturing from interfaces at any level of hierarchy within your design.  For stimulus generation Questa VIP provides sequences and scenarios for constrained random generation as well as integration with the inFact algorithmic stimulus generation.  For coverage closure Questa VIP also provides coverage models and test plans to help ensure adequate testing.  These features allow verification teams to reuse design checking provided by environments and reuse coverage models from block level to top level simulation to accelerate coverage closure.

What You Will Learn

  • VIP use for generating stimulus in active mode
  • VIP use to capture bus activity for environment use in passive mode
  • VIP stimulus and scenarios provided and integration with inFact
  • VIP test plan and coverage model use in determining coverage closure 

About the Presenter

Presenter Image Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Who Should View

  • Verification Engineers and Managers

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