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Introducing ModelSim DE, Support for Xilinx SecureIP and Assertion-Based Verification with SystemVerilog and PSL

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Overview

The webinar will introduce you to the features and capabilities now available in ModelSim DE, including support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support.

You already know that ModelSim is the simulator of choice for leading electronics companies in all industries. In addition to native compile, single kernel simulation technology, an intuitive, easy-to-use GUI, integrated project management, source code templates and wizards, ModelSim now offers support for Xilinx SecureIP and assertion-based verification with SystemVerilog and PSL support.

 

About the Presenter

Presenter Image Walter Gude

Walter has over 25 years of experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various ASIC projects including time spent in Munich Germany and Helsinki Finland. For the last decade, Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.

Who Should View

  • Design and Verification engineers

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