On-demand Web Seminar
You will learn the essential skills needed to create a simulation environment and what tools are available to quickly debug the root cause of design failures. Debug flows using waveforms, graphical dataflow for design connectivity, waveform compare for determining failures or viewing and analyzing memories will be highlighted. This training will also show you what technical resources are available to expand your verification knowledge.
What You Will Learn
- Determine a simulation workflow
- Create a simulation environment
- Learn essential debug tools
- Learn how to use Code Coverage
- Where to find essential learning resources
About the Presenter
Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.
Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.
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