Using ModelSim to Improve Simulation Runtime and Debug Productivity

Details

Overview

In this webinar, you’ll discover how to significantly reduce simulation runtime and improve debug productivity using ModelSim from Mentor Graphics.

ModelSim’s integrated HDL support helps you reduce SoC design and verification time, tasks which typically consume as much as 70 percent of total development time. This comprehensive technical seminar will help get you started using traditional RTL debug features such as debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files and VCD stimulus.

What You Will Learn

  • Native compiled, Single Kernel Simulator technology
  • VHDL, Verilog, PSL, and SystemVerilog design
  • Intelligent, easy-to-use GUI with Tcl interface
  • Integrated project management, source code templates, and wizards
  • Wave viewing and comparison; objects, watch, and memory windows increase debug productivity
  • Code coverage

About the Presenter

Presenter Image Walter Gude

Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.

Who Should View

  • Design and Verification engineers

Related Resources

Multimedia

The 2012 Wilson Research Group Functional Verification Study

Every two years, Mentor Graphics commissions Wilson Research Group to conduct a broad, vendor-independent study of design verification practices around the world.  In this presentation, Harry Foster...…View On-demand Web Seminar

ModelSim Simulation of Waveforms and Debug Demo for Beginners

This training provides an overview of Mentor Graphic's ModelSim® software. You will learn the basics about simulation and how to simulate with projects. You will learn how to work with multiple libraries...…View Product Demo

ModelSim to Questa Core: Adopting Assertion-Based Verification to Improve Your FPGA Debug and Design Quality

Learn how Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL).…View On-demand Web Seminar

Other Related Resources

Understanding DO-254 and Solutions to Facilitate Compliance

White Paper: RTCA/DO-254 (also known as DO-254 in the US or ED-80 in Europe) provides guidelines to facilitate requirements-based design of airborne electronic hardware. Now mandated by the US Federal Aviation Association...…View White Paper

Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper

ModelSim DE Evaluation Software

Software Evaluation: Introducing ModelSim DE. Debug productivity and observability in a ModelSim package.…View Software Evaluation