On-demand Web Seminar
Abstract
This comprehensive technical webinar will show you how to improve time-to-market for complex SoC designs through reduced simulation runtime and process debugs, thanks to Mentor Graphics ModelSim’s integrated simulation technology.
Duration: 25:25
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Overview
In this webinar, you’ll discover how to significantly reduce simulation runtime and improve debug productivity using ModelSim from Mentor Graphics.
ModelSim’s integrated HDL support helps you reduce SoC design and verification time, tasks which typically consume as much as 70 percent of total development time. This comprehensive technical seminar will help get you started using traditional RTL debug features such as debugging Verilog deltas, process debugging, tracing through source code, comparing results of waveform files and VCD stimulus.
What You Will Learn
- Native compiled, Single Kernel Simulator technology
- VHDL, Verilog, PSL, and SystemVerilog design
- Intelligent, easy-to-use GUI with Tcl interface
- Integrated project management, source code templates, and wizards
- Wave viewing and comparison; objects, watch, and memory windows increase debug productivity
- Code coverage
About the Presenter
Walter Gude
Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.
Who Should View
- Design and Verification engineers