ModelSim to Questa Core: Adopting Assertion-Based Verification to Improve Your FPGA Debug and Design Quality

Overview

The size and advanced features in today’s FPGAs have increased dramatically to a point where they can now compete with capabilities traditionally offered by ASICs alone. Accompanying all of these features and capabilities is a complexity in verification which traditional FPGA design flows are generally not prepared to address. Adopting assertion-based verification (ABV) can improve design quality through providing a “window” allowing active monitoring of functional correctness deep inside the design. Assertions catch errors that tests activate but fail to propagate to typical observation points; such as the primary outputs or interface signals. The assertions also turbo-charge time-to-debug productivity because they identify functional bugs much closer to the root cause; significantly shortening the causality traceback by hours or even days. Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL).

Mentor Graphics has taken a leadership role in both tools and methodology supporting Advanced Functional Verification and ABV is a key component. Viewing and developing assertions as part of the design and verification flow is natively supported in the Questa® Core GUI. Existing ModelSim users will have the same user friendly debug environment that they know and love, but with extra features turned on to help them create and use assertions for maximum productivity.

What You Will Learn

• The value of Assertion-Based Verification in your FPGA design flow
• Overview of the language and constructs for using assertions
• Overview of the debug and GUI capabilities in Questa® Core for using and debugging assertions
• Demonstration of assertions in action and an example of a typical hard to find bug/problem that they are capable of easily identifying

Who Should View

• Design and Verification Engineers and Managers