ModelSim to Questa Core: Adopting Assertion-Based Verification to Improve Your FPGA Debug and Design Quality
On-demand Web Seminar
The size and advanced features in today’s FPGAs have increased dramatically to a point where they can now compete with capabilities traditionally offered by ASICs alone. Accompanying all of these features and capabilities is a complexity in verification which traditional FPGA design flows are generally not prepared to address. Adopting assertion-based verification (ABV) can improve design quality through providing a “window” allowing active monitoring of functional correctness deep inside the design. Assertions catch errors that tests activate but fail to propagate to typical observation points; such as the primary outputs or interface signals. The assertions also turbo-charge time-to-debug productivity because they identify functional bugs much closer to the root cause; significantly shortening the causality traceback by hours or even days. Questa® Core enables ABV through support of SystemVerilog Assertion (SVA) constructs and the Property Specification Language (PSL).
Mentor Graphics has taken a leadership role in both tools and methodology supporting Advanced Functional Verification and ABV is a key component. Viewing and developing assertions as part of the design and verification flow is natively supported in the Questa® Core GUI. Existing ModelSim users will have the same user friendly debug environment that they know and love, but with extra features turned on to help them create and use assertions for maximum productivity.
What You Will Learn
- The value of Assertion-Based Verification in your FPGA design flow
- Overview of the language and constructs for using assertions
- Overview of the debug and GUI capabilities in Questa® Core for using and debugging assertions
- Demonstration of assertions in action and an example of a typical hard to find bug/problem that they are capable of easily identifying
About the Presenter
Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Mentor Graphics responsible for simulation with Questa and ModelSim. Prior to Mentor Graphics, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.
Who Should View
- Design and Verification Engineers and Managers
Injecting Automation into Verification - Assertions
What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way...…
Other Related Resources
FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
White Paper: This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...…
Free ModelSim PE Evaluation Software
Software Evaluation: Now is your opportunity for a risk free 21-day trial of the industry’s leading simulator with full mixed language support for VHDL, Verilog and SystemVerilog and a comprehensive debug environment...…